SC2200UFH-300 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300 Datasheet - Page 337
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SC2200UFH-300
Manufacturer Part Number
SC2200UFH-300
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.SC2200UFH-300.pdf
(429 pages)
Specifications of SC2200UFH-300
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC2200UFH-300F
Manufacturer:
NSC
Quantity:
201
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Video Processor Module - Video Processor Registers - Function 4
AMD Geode™ SC2200 Processor Data Book
Offset 44h-47h
Signature values stored in this register can be read by the host. This register is used for test purposes.
Offset 48h-4Bh
Offset 4Ch-4Fh
31:16
31:22
21:20
19:18
17:16
15:14
31:8
15:8
Bit
7:3
7:0
2
1
0
Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Description
SIG_VALUE (Signature Value). (Read Only) A 24-bit signature value is stored in this bit field and can be read at any time.
The signature is produced from the RGB data output of the mixer. This bit field is used for test purpose only.
See SIGN_EN (bit 0) description for more information.
Reserved.
SIGN_FREE (Signature Free Run).
0: Disable. (Default) If this bit was previously set to 1, the signature process stops at the end of the current frame (i.e., at
1: Enable. If SIGN_EN (bit 0) = 1, the signature register captures data continuously across multiple frames.
Reserved.
SIGN_EN (Signature Enable).
0: Disable. (Default) The SIG_VALUE (bits [31:8]) is reset to 000001h and held (no capture).
1: Enable. The next falling edge of VSYNC is counted as the start of the frame to be used for CRC checking with each pixel
After a signature capture, the SIG_VALUE can be read to determine the CRC check status. SIGN_EN can then be reset to
initialize the SIG_VALUE as an essential preparation for the next round of CRC check.
Reserved.
REV_ID (Revision ID). See device specification update for value.
DEV_ID (Device ID). See device specification update for value.
Reserved.
ALPHA3_WIN_PRIORITY (Alpha Window 3 Priority). Determines the priority of Alpha Window 3. A higher number indi-
cates a higher priority. Priority is used to determine display order for overlapping alpha windows.
00: Lowest priority (default).
01: Medium priority.
10: Highest priority.
11: Illegal.
Note:
ALPHA2_WIN_PRIORITY (Alpha Window 2 Priority). Determines the priority of Alpha Window 2. A higher number indi-
cates a higher priority. Priority is used to determine display order for overlapping alpha windows.
00: Lowest priority (default).
01: Medium priority.
10: Highest priority.
11: Illegal.
Note:
ALPHA1_WIN_PRIORITY (Alpha Window 1 Priority). Determines the priority of Alpha Window 1. A higher number indi-
cates a higher priority. Priority is used to determine display order for overlapping alpha windows.
00: Lowest priority (default).
01: Medium priority.
10: Highest priority.
11: Illegal.
Note:
Reserved.
the next falling edge of VSYNC).
clock beginning with the next VSYNC.
If SIGN_FREE (bit 2) = 1, the signature register captures the pixel data signature continuously across multiple frames.
If SIGN_FREE (bit 2) = 0, a signature is captured for one frame at a time, starting from the next falling VSYNC.
Priority of enabled alpha windows must be different.
Priority of enabled alpha windows must be different.
Priority of enabled alpha windows must be different.
Video De-Interlacing and Alpha Control Register (R/W)
Device and Revision Identification (RO)
CRC Signature Register (R/W)
32580B
Reset Value: xxxxx100h
Reset Value: 0000xxxxh
Reset Value: 00060000h
349
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