SC2200UFH-300 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300 Datasheet - Page 218

• Manufacturer Part Number: SC2200UFH-300
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

226
Index CDh
Index CEh
Index CFh
Index D0h
Index D1h-EBh
Index ECh
Index EDh-F3h
Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
6:0
6:0
6:0
7:0
7:0
7
7
Description
Mask.
If bit 7 = 0 (I/O):
If bit 7 = 1 (Memory):
Note:
Memory or I/O Mapped. determines how User Defined Device 2 is mapped.
0: I/O
1: Memory
Mask.
If bit 7 = 0 (I/O):
If bit 7 = 1 (Memory):
Note:
Memory or I/O Mapped. Determines how User Defined Device 3 is mapped.
0: I/O.
1: Memory.
Mask.
If bit 7 = 0 (I/O):
If bit 7 = 1 (Memory):
Note:
Software SMI. A write to this location generates an SMI. The data written is irrelevant. This register allows software entry
into SMM via normal bus access instructions.
Timer Test Value. The Timer Test register is intended only for test and debug purposes. It is not intended for setting opera-
tional timebases. For normal operation, never write to this register.
A “1” in a mask bit means that the address bit is ignored for comparison.
A “1” in a mask bit means that the address bit is ignored for comparison.
A “1” in a mask bit means that the address bit is ignored for comparison.
Bit 6
Bit 5
Bits [4:0] Mask for address bits A[4:0]
Bits [6:0] Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.
Bit 6
Bit 5
Bits [4:0] Mask for address bits A[4:0]
Bits [6:0] Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.
Bit 6
Bit 5
Bits [4:0] Mask for address bits A[4:0]
Bits [6:0] Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.
32580B
0: Disable write cycle tracking
1: Enable write cycle tracking
0: Disable read cycle tracking
1: Enable read cycle tracking
0: Disable write cycle tracking
1: Enable write cycle tracking
0: Disable read cycle tracking
1: Enable read cycle tracking
0: Disable write cycle tracking
1: Enable write cycle tracking
0: Disable read cycle tracking
1: Enable read cycle tracking
User Defined Device 2 Control Register (R/W)
User Defined Device 3 Control Register (R/W)
Software SMI Register (WO)
Timer Test Register (R/W)
Reserved
Reserved
Reserved
Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0
AMD Geode™ SC2200 Processor Data Book
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h