WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 302

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

10.2.2.26
10.2.2.27
10.2.2.28
10.2.2.29
10.2.3
10.2.3.1
302
Software Flash Burst Data Register - FLSWDATA (0x1034; RW)
Software Flash Burst Access Counter - FLSWCNT (0x1038; RW)
Flash Opcode Register - FLOP (0x0103C; RW)
This register is used by the 82574 to initiate the appropriate instructions to the NVM
device.
FEEP Auto Load - FLOL (0x01050; RW)
PCIe Register Descriptions
3GIO Control Register - GCR (0x05B00; RW)
NVDATA
Abort
Reserved
NVCNT
RAM_PWR_
SAVE_EN
Reserved
Reserve
Disable_
timeout_
mechanism
Self_test_
result
Gio_good_l0s
Gio_dis_rd_
err
Field
Field
Field
Field
31:0
31
30:25
24:0
0
7:1
31:8
31
30
29
28
Bit(s)
Bit(s)
Bit(s)
Bit(s)
0x0
0b
0x0
0x0
1b
0x0
0x0
0b
0b
0b
0b
Default
Default
Default
Initial
Value
Write NVM Data
Data written to the NVM.
Abort
Writing a 1b to this bit aborts the current burst operation. It is self-
cleared by the Flash interface block when the Abort command has
been executed. Abort request is not permitted after writing the last
Dword.
Reserved
NVM Counter
This counter holds the size of the Flash burst read or write in Dwords
and is also used as the write byte count but in this case it is byte
count.
When set to 1b, enables reduced power consumption by clock gating
the 82574 RAMs.
Auto loaded from NVM 0x11 bits 7:1.
Reserved
If set, the PCIe time-out mechanism is disabled.
If set, a self-test result finished successfully.
Force good PCIe L0s training.
Disable running disparity error of PCIe 108b decoders.
82574 GbE Controller—Driver Programing Interface
Description
Description
Description
Description