WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 5

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Datasheet—82574 GbE Controller
8.0
7.2
7.3
7.4
7.5
7.6
7.7
System Manageability............................................................................................ 188
8.1
8.2
8.3
8.4
8.5
8.6
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10 Receive Packet Checksum Offloading ...................................................... 137
7.1.11 Multiple Receive Queues and Receive-Side Scaling (RSS)........................... 139
Packet Transmission ........................................................................................ 145
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10 Transmit Descriptor Formats.................................................................. 152
7.2.11 Extended Data Descriptor Format ........................................................... 160
TCP Segmentation ........................................................................................... 164
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
Interrupts ...................................................................................................... 170
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
802.1q VLAN Support ...................................................................................... 176
7.5.1
7.5.2
7.5.3
LED's............................................................................................................. 178
Time SYNC (IEEE1588 and 802.1AS) ................................................................. 179
7.7.1
7.7.2
7.7.3
7.7.4
Scope ............................................................................................................ 188
Pass-Through (PT) Functionality ........................................................................ 188
Components of a Sideband Interface.................................................................. 189
SMBus Pass-Through Interface.......................................................................... 189
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
Receive TCO Flow............................................................................................ 205
Transmit TCO Flow .......................................................................................... 205
Packet Split Receive Descriptor .............................................................. 128
Receive Descriptor Fetching ................................................................... 131
Receive Descriptor Write Back................................................................ 131
Receive Descriptor Queue Structure........................................................ 132
Receive Interrupts................................................................................ 134
Transmit Functionality........................................................................... 145
Transmission Flow Using Simplified Legacy Descriptors.............................. 146
Transmission Process Flow Using Extended Descriptors.............................. 146
Transmit Descriptor Ring Structure ......................................................... 147
Multiple Transmit Queues ...................................................................... 149
Overview of On-Chip Transmit Modes...................................................... 149
Pipelined Tx Data Read Requests ............................................................ 150
Transmit Interrupts .............................................................................. 151
Transmit Data Storage .......................................................................... 151
TCP Segmentation Performance Advantages ............................................ 164
Ethernet Packet Format......................................................................... 164
TCP Segmentation Data Descriptors........................................................ 165
TCP Segmentation Source Data .............................................................. 166
Hardware Performed Updating for Each Frame ......................................... 166
TCP Segmentation Use of Multiple Data Descriptors .................................. 167
Legacy and MSI Interrupt Modes ............................................................ 170
MSI-X Mode......................................................................................... 170
Registers............................................................................................. 171
Interrupt Moderation ............................................................................ 173
Clearing Interrupt Causes...................................................................... 175
802.1q VLAN Packet Format .................................................................. 176
Transmitting and Receiving 802.1q Packets ............................................. 177
802.1q VLAN Packet Filtering ................................................................. 177
Overview ............................................................................................ 179
Flow and Hardware/Software Responsibilities ........................................... 180
Hardware Time Sync Elements ............................................................... 182
PTP Packet Structure ............................................................................ 185
General............................................................................................... 190
Pass-Through Capabilities...................................................................... 190
Manageability Receive Filtering............................................................... 191
SMBus Transactions.............................................................................. 198
SMBus Notification Methods ................................................................... 202
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