WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 74

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

4.5
4.5.1
Table 30.
4.5.2
74
Timing Parameters
Timing Requirements
The 82574 requires the following start-up and power state transitions.
Timing Requirements
MDIO and NVM Semaphore
The MDIO and NVM semaphore mechanism resolved possible conflicts between
software and hardware access to the MDIO and NVM (the later applies only to software
accesses through the EERD register). The mechanism does not block software accesses
to MDIO or NVM, therefore enabling software to use or ignore this process at will. For
example, software might track the hardware state through other means (such as, a
software state machine) and avoid any MDIO and NVM accesses when hardware is in
configuration states. However, hardware must comply with the protocol.
The MDIO software Ownership bit, MDIO manageability Ownership bit and the MDIO
hardware Ownership bit provide a mechanism for software, manageability and
hardware responses to arbitrate for accesses to MDIO and NVM. Software arbitration
for NVM accesses is only required when done through the EERD register. A request for
ownership is registered by writing a 1b into the respective bit (software writes to the
MDIO software Ownership bit, manageability writes to the manageability Ownership bit
and hardware writes to the MDIO hardware Ownership bit). The requesting agent is
granted access when the same bit is read as 1b (such as, access is not granted as long
as the bit is 0b). The MDIO software Ownership and the MDIO hardware Ownership bits
are cleared on reset, while the MDIO manageability Ownership bit is reset only by
LAN_PWR_GOOD (or if the firmware clears it). The 82574 guarantees that at any given
time at most only one bit is 1b. Access is granted when a bit is actually written with 1b
and the other bits are 0b. If all agents request access at the same time, priority order is
manageability, software and then hardware. Once the access completes, the controlling
agent must write a 0b to its ownership bit to enable accesses by the other agents.
The 82574’s hardware sets the bit while loading the extended configuration area.
Parameter
txog
tPWRGD-
CLK
tPVPGL
Tpgcfg
td0mem
tl2pg
tl2clk
Tclkpg
Tpgdl
Xosc stable from power stable
PCIe clock valid to PCIe power good
Power rails stable to PCIe PE_RST_N
inactive
External PE_RST_N signal to first
configuration cycle.
Device programmed from D3h to D0
state to next device access
L2 link transition to PE_RST_N
assertion
L2 link transition to removal of PCIe
reference clock
PE_RST_N assertion to removal of PCIe
reference clock
PE_RST_N assertion time
Description
100 s
100 ms
100 ms
10 ms
0 ns
100 ns
0 ns
100 s
Min
10 ms
-
-
Max
82574 GbE Controller—Initialization
According to PCIe specification.
According to PCIe specification.
According to PCIe specification.
According to PCI power
management specification.
According to PCIe specification.
According to PCIe specification.
According to PCIe specification.
According to PCIe specification.
Notes