WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet
WG82574L S LBA9
Specifications of WG82574L S LBA9
Related parts for WG82574L S LBA9
WG82574L S LBA9 Summary of contents
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... GB of physical memory — Programmable host memory receive buffers (256 bytes to 16 KB) — Intelligent interrupt generation features to enhance driver performance — Descriptor ring management hardware for transmit and receive software controlled reset ...
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... Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548- 4725 to: http://www ...
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... Host I/F ................................................................................................ 37 3.1.6 Error Events and Error Reporting .............................................................. 38 3.1.7 Link Layer ............................................................................................. 41 3.1.8 PHY ...................................................................................................... 42 3.1.9 Performance Monitoring .......................................................................... 43 3.2 Ethernet Interface ............................................................................................. 43 3.2.1 MAC/PHY GMII/MII Interface ................................................................... 43 3.2.2 Duplex Operation for Copper PHY/GMII/MII Operation ................................. 44 3.2.3 Auto-Negotiation & Link Setup Features .................................................... 45 3.2.4 Loss of Signal/Link Status Indication ......................................................... 48 3.2.5 10/100 Mb/s Specific Performance Enhancements ...
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System Management Bus (SMBus) .......................................................................60 3.5 NC-SI...............................................................................................................60 3.5.1 Interface Specification .............................................................................61 3.5.2 Electrical Characteristics ..........................................................................61 4.0 Initialization ............................................................................................................62 4.1 Introduction ......................................................................................................62 4.2 Reset Operation.................................................................................................62 4.3 Power Up..........................................................................................................64 4.3.1 Power-Up Sequence ................................................................................64 4.3.2 Timing Diagram......................................................................................72 4.4 Global Reset (PE_RST_N, PCIe ...
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... Extended Data Descriptor Format ........................................................... 170 7.3 TCP Segmentation ........................................................................................... 174 7.3.1 TCP Segmentation Performance Advantages ............................................ 174 7.3.2 Ethernet Packet Format......................................................................... 174 7.3.3 TCP Segmentation Data Descriptors........................................................ 175 7.3.4 TCP Segmentation Source Data .............................................................. 176 7.3.5 Hardware Performed Updating for Each Frame ......................................... 176 7 ...
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... Terminology......................................................................................... 238 8.11.2 System Topology .................................................................................. 240 8.11.3 Data Transport ..................................................................................... 241 8.12 NC-SI Support................................................................................................. 243 8.12.1 Supported Features............................................................................... 243 8.12.2 NC-SI Mode - Intel Specific Commands.................................................... 244 8.13 Basic NC-SI Workflows ..................................................................................... 249 8.13.1 Package States..................................................................................... 249 8.13.2 Channel States ..................................................................................... 250 8.13.3 Discovery ............................................................................................ 250 8 ...
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... Crystal Support............................................................................................... 437 13.3.1 Crystal Selection Parameters ................................................................. 437 13.3.2 Crystal Placement and Layout Recommendations...................................... 440 13.4 Oscillator Support............................................................................................ 441 13.4.1 Oscillator Placement and Layout Recommendations................................... 443 13.5 Ethernet Interface ........................................................................................... 444 13.5.1 Magnetics for 1000 BASE-T.................................................................... 444 13.5.2 Magnetics Module Qualification Steps ...................................................... 444 7 ...
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... Third-Party Magnetics Manufacturers ....................................................... 444 13.5.4 Designing the 82574 as a 10/100 Mb/s Only Device .................................. 445 13.5.5 Layout Considerations for the Ethernet Interface....................................... 446 13.5.6 Physical Layer Conformance Testing ........................................................ 452 13.5.7 Troubleshooting Common Physical Layout Issues ...................................... 452 13.6 SMBus and NC-SI ............................................................................................ 453 13 ...
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... February 2009 2.4 • Updated table 66. • Added section 8.12.2.3 - Set Intel Management Control Formats. • Added section 8.12.3.4 - Get Intel Management Control Formats. • Added section 10.2.3.12 - 3GPIO Control Register 2 - GCR2. December 2008 2.3 • Updated section 13.1.4 - PCIe Routing. ...
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... Updated Sections 12, and 13; as indicated by the change bars in the left margin. • Updated Sections 10, and 12. August 2007 0.7 • Added Sections 13, 14, 15, and 16. • Added Section 12.0 “Electrical Specifications”. July 2007 0.6 • Updated Section 2.0 “Pin Interface”. June 2007 0.5 Initial release (Intel Confidential). 10 82574 GbE Controller—Datasheet ...
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Datasheet—82574 GbE Controller Note: This page intentionally left blank. 11 ...
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... Introduction The 82574 family (82574L and 82574IT) are single, compact, low power components that offer a fully-integrated Gigabit Ethernet Media Access Control (MAC) and Physical Layer (PHY) port. The 82574L uses the PCI Express* (PCIe*) architecture and provides a single-port implementation in a relatively small area so it can be used for server and client configurations as a LAN on Motherboard (LOM) design ...
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... The 4-byte or 16-byte address that designates the Ethernet controller within the IP communication protocol. This address is dynamic and can be updated frequently during runtime. Intelligent Platform Management Interface Specification. Local Area Network. Also known as the Ethernet. The 6-byte address that designates Ethernet controller within the Ethernet protocol. ...
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... I C Specification NC-SI Specification Other reference documents include: • Intel® 82574 Family GbE Controller Specification Update, Intel Corporation. • PCI Express* Specification v2.0 (2.5 GT/s) • Advanced Configuration and Power Interface Specification • PCI Bus Power Management Interface Specification 14 Definition System Management Bus ...
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... Features Summary This section describes the 82574’s features that were present in previous Intel client GbE controllers and those features that are new to the 82574. SMBus SMBus ...
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... GB of physical memory Programmable host memory receive buffers (256 bytes to 16 KB) Intelligent interrupt generation features to enhance software device driver performance Descriptor ring management hardware for transmit and receive Software controlled reset (resets everything ...
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Introduction—82574 GbE Controller Table 3. Manageability Features Feature NC-SI over RMII for remote management core SMBus advanced pass through Table 4. Performance Features Feature Configurable receive and transmit data FIFO; programmable increments TCP segmentation capability compatible with ...
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... Table 6. Product Ordering Codes Part Number Intel® 82574L Gigabit Network WG82574L Connection Intel® 82574IT Gigabit Network WG82574IT Connection 18 82574 GbE Controller—Introduction Product Name • Embedded and Entry Server GbE LAN. ...
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Introduction—82574 GbE Controller Note: This page intentionally left blank. 19 ...
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Pin Interface 2.1 Pin Assignments The 82574L supports a 64-pin QFN package with an Exposed Pad* (e-Pad*). Note that the e-Pad is ground MDI_MINUS[3] 50 MDI_PLUS[3] 51 AVDD1p9 52 MDI_MINUS[2] 53 MDI_PLUS[2] 54 MDI_MINUS[1] ...
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Pin Interface—82574 GbE Controller 2.2 Pull-Up/Pull-Down Resistors and Strapping Options • As stated in the Name and Function table columns, the internal Pull-Up/Pull-Down (PU/PD) resistor values are 30 K ± 50%. • Only relevant (digital) pins are listed; analog or ...
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Table 7. PCIe Symbol Lead # PE_Rp 24 23 PE_Rn PE_WAKE_N/ 16 JTAG_TDO PE_RST_N 17 2.3.2 NVM Port Table 8. NVM Port Symbol Lead # NVM_SI 12 NVM_SO 14 NVM_SK 13 NVM_CS_N 15 22 82574 GbE Controller—Pin Interface Op Type ...
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Pin Interface—82574 GbE Controller 2.3.3 System Management Bus (SMBus) Interface Table 9. SMBus Interface Symbol SMB_DAT SMB_CLK SMB_ALRT_N Note: If the SMBus is disconnected, an external pull-up should be used for these pins, unless it is guaranteed that manageability is ...
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Table 10. NC-SI and Testability Symbol Lead # AUX_PWR/ 39 JTAG_TCK NVMT/JTAG_TMS 38 JTAG_TDI 40 2.3.5 LEDs Table 11 lists the functionality of each LED output pin. The default activity of each LED can be modified in the NVM. The ...
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Pin Interface—82574 GbE Controller Table 12. PHY Pins Symbol MDI_PLUS[0] MDI_MINUS[0] MDI_PLUS[1] MDI_MINUS[1] MDI_PLUS[2] MDI_MINUS[2] MDI_PLUS[3] MDI_MINUS[3] XTAL1 XTAL2 ATEST_P ATEST_N RSET 2.3.7 Miscellaneous Pin Table 13. Miscellaneous Pin Symbol DEV_OFF_N 28 Op Lead # Type Mode Media Dependent Interface[0]: ...
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Power Supplies and Support Pins 2.3.8.1 Power Support Table 14. Power Support Symbol CTRL10 62 CTRL19 64 DIS_REG10 59 2.3.8.2 Power Supply Table 15. Power Supply Symbol Lead # 4, 11, 18, 27, VDD1p0 37, 41, 60 22, 44, ...
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Pin Interface—82574 GbE Controller 2.4 Package The 82574L supports a 64-pin QFN package with e-Pad. package schematics. Figure 3. 82574L QFN Package Figure 3 shows the 27 ...
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Interconnects 3.1 PCIe PCIe is a third generation I/O architecture that enables cost competitive, next generation I/O solutions providing industry leading price/performance and feature richness industry-driven specification. PCIe defines a basic set of requirements that comprehends ...
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Interconnects—82574 GbE Controller A packet is the fundamental unit of information exchange and the protocol includes a message space to replace the number of side-band signals found on many of today’s buses. This movement of hard-wired signals from the physical ...
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Physical Interface Properties • Point to point interconnect — Full-duplex; no arbitration • Signaling technology: — Low voltage differential — Embedded clock signaling using 8b/10b encoding scheme • Serial frequency of operation: 2.5 GHz. • Interface width of one ...
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Interconnects—82574 GbE Controller Transaction Type Memory Write Request I/O Read Request I/O Write Request Read Completions Message Flow control types: • Posted request headers • Posted request data payload • NPH - Non-posted request headers • ...
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Table 18. Supported Message in The 82574L (As a Receiver) Message Routing code [7:0] r2r1r0 0x14 100 0x19 011 0x41 100 0x43 100 0x40 100 0x45 100 0x47 100 0x44 100 0x50 100 0x7E 010,011,100 0x7E 010,011,100 0x7F 010,011,100 0x7F ...
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Interconnects—82574 GbE Controller 3.1.3.5 Data Alignment 4 KB Boundary: Requests must never specify an address/length combination that causes a memory space access to cross boundary hardware’s responsibility to break requests into 4 KB-aligned requests (if ...
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Transaction Attributes 3.1.3.8.1 Traffic Class (TC) and Virtual Channels (VC) The 82574L supports only and (default). 3.1.3.8.2 Relaxed Ordering The 82574L takes advantage of the relaxed ordering rules in PCIe by setting the ...
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Interconnects—82574 GbE Controller 3.1.3.9 Error Forwarding If a Transaction Layer Protocol (TLP) is received with an error-forwarding trailer, the packet is dropped and not delivered to its destination. The 82574L does not initiate any additional master requests for that PCI ...
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Table 20. Allocation of FC Credits Credit Type Posted Request Header (PH) Posted Request Data (PD) Non-Posted Request Header (NPH) Non-Posted Request Data (NPD) Completion Header (CPLH) Completion Data (CPLD) Rules for FC updates: • The 82574L maintains two credits ...
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... TX: RD REQ data 0 from main memory to Ethernet 09 TX: RD REQ data 1 from main memory to Ethernet 0A TX: RD REQ data 2 from main memory to Ethernet 0B TX: RD REQ data 3 from main memory to Ethernet 0C RX: RD REQ to bring Descriptor to core second Queue 0E RX: WR REQ to write back descriptor from core to memory (second queue) 10 ...
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... In this case the host interface role is to sort the request completions and transfer them to the Ethernet core in the correct order. 3.1.6 Error Events and Error Reporting 3 ...
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Interconnects—82574 GbE Controller Device Control :: Correctable Error Reporting Enable Device Control :: Unsupported Request Reporting Enable Device Control :: Non-Fatal Error Reporting Enable Device Control :: Fatal Error Reporting Enable Parity Error Response Rcv Msg Error Message Processing Secondary ...
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Error Name Data link layer Violations of Flow Control protocol error initialization protocol TLP errors Poisoned TLP TLP with Error Forwarding received • Wrong config access • MRdLk • Config Request Type1 • Unsupported vendor • Not valid MSG code ...
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Interconnects—82574 GbE Controller 3.1.6.1.2 Error Pollution Error pollution can occur if error conditions for a given transaction are not isolated to the error's first occurrence. If the PHY detects and reports a receiver error, to avoid having this error propagate ...
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Table 24. DLLPs initiated by The 82574L Remarks ACK NAK PM_Enter_L1 PM_Enter_L23 PM_Active_State_Request_L1 InitFC1-P InitFC1-NP InitFC1-Cpl InitFC2-P InitFC2-NP InitFC2-Cpl UpdateFC-P UpdateFC-NP 1. UpdateFC-Cpl is not sent because of the infinite FC-Cpl allocation. 3.1.7.3 Transmit EDB Nullifying In case of a ...
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... The 82574L MAC is optimized for full-duplex operation in 1000 Mb/s mode. Half-duplex 1000 Mb/s operation is not supported. The PHY features 10/100/1000-BaseT signaling and is capable of performing intelligent power-management based on both the system power-state and LAN energy-detection (detection of unplugged cables). Power management includes the ability to shutdown ...
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... MAC register bits STATUS.SPEED each time MAC speed has not been forced. • MAC Dx power state indication - The MAC indicates its ACPI power state (PWR_STATE) to the PHY to enable it to perform intelligent power-management (provided that the PHY power-management is enabled in the MAC CTRL register). 3.2.2 ...
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Interconnects—82574 GbE Controller 3.2.2.1 Full Duplex All aspects of the IEEE 802.3, 802.3u, 802.3z, and 802.3ab specifications are supported in full duplex operation. Full duplex operation is enabled by several mechanisms, depending on the speed configuration of the 82574 and ...
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The PHY performs auto-negotiation per 802.3ab clause 40 and extensions to clause 28. Link resolution is obtained by the MAC from the PHY after the link has been established. The MAC accomplishes this via the MDIO interface, via specific signals ...
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Interconnects—82574 GbE Controller 3.2.3.1.2 MAC Speed Resolution For proper link operation, both the MAC and PHY must be configured for the same speed of link operation. The speed of the link can be determined and set by several methods with ...
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When MAC speed is neither forced nor auto-sensed by the MAC, the current MAC speed setting and the speed indicated by the PHY is reflected in the Device Status register bits STATUS.SPEED. 3.2.3.1.3 MAC Full/Half Duplex Resolution The duplex configuration ...
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... The 82574L contains an Adaptive IFS register (see implementation of a driver-based adaptive IFS algorithm for collision reduction, which is similar to Intel's other Ethernet products (such as PRO/100 adapters). Adaptive IFS throttles back-to-back transmissions in the transmit MAC and delays their transfer to the CSMA/CD transmit function and then can be used to delay the transmission of back-to-back packets on the wire ...
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Flow Control Flow control as defined in 802.3x, as well as the specific operation of asymmetrical flow control defined by 802.3z, are supported in the MAC. The following seven registers are defined for the implementation of flow control: • ...
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Interconnects—82574 GbE Controller Figure 6. 802.3x MAC Control Frame Format Where S is the start-of-packet delimiter and T is the first part of the end-of-packet delimiters for 802.3z encapsulation. The receiver is enabled to receive flow control frames if flow ...
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Discard Pause Frames and Pass MAC Control Frames Two bits in the Receive Control register are implemented specifically for control over receipt of pause and MAC control frames. These bits are Discard PAUSE Frames (DPF) and Pass MAC Control ...
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... Supported NVM Devices Some Intel LAN controllers require both an EEPROM and Flash device for storing LAN data. However, the 82574 reduces the Bill of Material (BOM) cost by consolidating the EEPROM and Flash into a single non-volatile memory device. The NVM is connected to a single Serial Peripheral Interface (SPI) ...
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Table 25. NVM Configuration Size Configuration SMBus or NC-SI manageability No Manageability/No iSCSI boot PXE only iSCSI boot only Both iSCSI boot and PXE 1. If PXE and iSCSI boot firmware is required, they must be integrated into the BIOS. ...
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Interconnects—82574 GbE Controller 3.3.4 Device Operation with an External EEPROM When the 82574 is connected to an external EEPROM, it provides similar functionality to its predecessors with the following enhancements: • Enables a complete parallel interface for read/write to the ...
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Address 8K Address 4K Address 00 Figure 7. NVM Shadow RAM 3.3.6.1 Flash Mode The 82574L is initialized from the NVM. As part of the initialization sequence, the 82574 copies the 4 KB content from the ...
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Interconnects—82574 GbE Controller 3.3.7 NVM Clients and Interfaces There are several clients that might access the NVM or shadow RAM listed in the following table. Listed are the various clients and their access type to the NVM: software device driver, ...
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Note: When software accesses the EEPROM or Flash spaces via the bit banging interface, it should follow these steps: 1. Write the Request bit in the FLA or EEC registers. 2. Poll the Grant bit in the ...
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Interconnects—82574 GbE Controller Case 2 - The 82574L is connected to a physical Flash device: 1. The 82574L writes the data to the shadow RAM and sets the Done bit in the EEWR register. 2. Update of the shadow RAM ...
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Until new data is written to the FLSWDATA register, the Flash clock is paused. 9. Once data is written to the FLSWDATA by the software, the DONE bit in the FLSWCTL register is cleared and is set after hardware ...
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Interconnects—82574 GbE Controller MC LLC - LOGICAL LINK CONTROL MAC - MEDIA ACCESS CONTROL RECONCILIATION Figure 8. NC-SI Interface 3.5.1 Interface Specification The 82574L NC-SI interface meets the RMII Specification, Rev. 1 PHY-side device. The following NC-SI capabilities ...
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Initialization 4.1 Introduction This chapter discusses initialization steps. This includes: • General hardware power-up state • Basic device configuration • Initialization of transmit and receive operation • Link configuration and software reset capability • Statistics initialization 4.2 Reset Operation ...
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Initialization—82574 GbE Controller • Force TCO - This reset is generated when manageability logic is enabled only generated if the reset on the Force TCO bit of the NVM's Management Control word is 1b. In pass-through mode it ...
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The Wake-Up Management (WUM) registers include the following: — Wake-up filter control. — IP address Valid. — IPv4 address table — IPv6 address table — Flexible filter length table — Flexible filter mask table 5. The following register fields ...
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Initialization—82574 GbE Controller Figure 9. 82574L Power Up - General Flow Start Power-On-Reset Flash EEPROM A Load Flash Load EEPROM C Initialize manageability and PHY D Read NVM after PERST# de-assertion E Initialize PCIe and PHY Bring up PCIe link ...
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Figure 10. 82574L Initialization - Power-On Reset 66 Start Power ramp up (3.3 V dc, 1.9 V dc, 1.05 V dc) Start Xosc stabe From power-up <10 Internal power-on- reset triggers From power-up <50 82574 samples NVMT strapping Determine NVM ...
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Initialization—82574 GbE Controller Read signature at word 2K+0x12 ~0 Bad signature 82574 set to default values Set EEC.Auto_RD 0 Figure 11. 82574L Initialization - Flash Load Notes sector is read in a single burst, so the ...
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Set EEC.Auto_RD 0 Figure 12. 82574L Initialization - EEPROM Load Each word is read separately using a 5-byte command (1 byte instruction, 2 byte address, and 2 byte data). Total time ...
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Initialization—82574 GbE Controller No need to load 82574 set to default values Clear SW/HW NVM semaphore 0 Figure 13. 82574L Initialization - PHY and Manageability Each PCIe register write takes ~20 PCIe clocks (31.25 MHz) per table entry <=> 640 ...
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Check valid Shadow and signature ~0 Load base area (0x00- 0x40) from Shadow RAM Set EEC.Auto_RD ~0.0032 Figure 14. 82574L Initialization - NVM Load After PE_RST_N 70 D PERST# is de-asserted by the platform PHY is powered down ~0 NVMT ...
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Initialization—82574 GbE Controller Load Extended Configuration from Shadow RAM Clear SW/HW NVM semaphore ~0.42 Figure 15. 82574L Initialization - PHY and PCIe E Enable the PHY PHY was in power-down during NVM load 11 Flash 4 Start PCIe link training ...
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Timing Diagram Power txo 1 g Xosc Power-On-Reset (internal) PCIe reference clock PERST# NVM Load PHY State PCIe Link up Manageability / Wake D-State Figure 16. Power-Up Timing Diagram Table 30. Notes to Power-Up Timing Diagram Note 1 Xosc ...
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Initialization—82574 GbE Controller 4.4 Global Reset (PE_RST_N, PCIe In-Band Reset) 4.4.1 Reset Sequence Figure 17 and Figure 18 de-assertion or PCIe in-band reset) and until the device is ready to accept host commands. Check valid Shadow and signature ~0 Load ...
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Load Extended Configuration from Shadow RAM Clear SW/HW NVM semaphore ~0.42 Figure 18. 82574L Global Reset - PHY and PCIe 4.4.2 Timing Diagram The following timing diagram shows the 82574’s behavior through a PE_RST_N reset Enable the PHY ...
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Initialization—82574 GbE Controller PCIe reference clock PERST# NVM Load PHY State Active PCIe Link up L0 Wake D-State Figure 19. Global Reset Timing Diagram Table 31. Notes to Global Reset Timing Diagram Note The system must assert PE_RST_N before stopping ...
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Timing Parameters 4.5.1 Timing Requirements The 82574L requires the following start-up and power state transitions. Table 32. Timing Requirements Parameter txog Xosc stable from power stable tPWRGD- PCIe clock valid to PCIe power good CLK Power rails stable to ...
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Initialization—82574 GbE Controller 4.6 Software Initialization Sequence The following sequence of commands is typically issued to the device by the software device driver in order to initialize the 82574 to normal operation. The major initialization steps are: 1. Disable Interrupts ...
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Interrupts During Initialization Most drivers disable interrupts during initialization to prevent re-entrancy. Interrupts are disabled by writing to the IMC register. Note that the interrupts need to be disabled also after issuing a global reset typical driver ...
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Initialization—82574 GbE Controller — CTRL.TFCE - Must be set by software after reading flow control resolution from PHY registers. — CTRL.SPEED - Don't care; speed setting is established from PHY's internal indication to the MAC (SPD_IND) after PHY has auto-negotiated ...
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MAC/PHY duplex and speed settings both forced by software (fully-forced link setup). (CTRL.FRCDPLX = 1b, CTRL.FRCSPD = 1b, CTRL.SLU = 1b) — CTRL.FD - Set by software to desired full-/half- duplex operation (must match duplex setting of the PHY). ...
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Initialization—82574 GbE Controller 4.6.5.1 Initialize the Receive Control Register To properly receive packets requires simply that the receiver is enabled. This should be done only after all other setup is accomplished. If software uses the Receive Descriptor Minimum Threshold Interrupt, ...
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Program the TIPG register with the following (decimal) values to get the minimum legal IPG: • IPGT = 8 • IPGR1 = 2 • IPGR2 = 10 Note: IPGR1 and IPGR2 are not needed in full-duplex, but it is easier ...
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Power Management and Delivery The 82574L supports the Advanced Configuration and Power Interface (ACPI 2.0) specification as well as Advanced Power Management (APM). This section describes how power management is implemented in the 82574. Implementation requirements were obtained from ...
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Power Management and Delivery—82574 GbE Controller 5.3 Power Delivery 82574L operates from the following power rails: • power rail for internal power regulation and for periphery. The 3 should be supplied by an external ...
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Internal Power On Reset assertion PE_RST_N assertion Figure 20. Power Management State Diagram 5.4.2 Auxiliary Power Usage If ADVD3WUC=1b, the 82574 uses the AUX_PWR indication that auxiliary power is available to the controller, and therefore advertises D3cold wake up support. ...
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Power Management and Delivery—82574 GbE Controller The AUX Power PM Enable bit in the PCIe Device Control register determines if the 82574 complies with the auxiliary power regime defined in the PCIe specification. If set, the 82574 might consume higher ...
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When entering the D0u state, the 82574 disables all wake ups and asserts a reset to the PHY while the NVM is being read. If the APM Mode bit in the NVM's Initialization Control Word 2 is set, then APM ...
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... D3 exit). Any transmit packets that were not sent, can still be transmitted (assuming the Ethernet link is up). To reduce power consumption, if any of ASF manageability, APM wake, and PCI-PM PME ...
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Dr State Transition to Dr state is initiated on three occasions: • At system power state begins with the assertion of the internal power detection circuit (Internal Power On Reset) and ends with the assertion of ...
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... Link-Disconnect In any of D0u, D0a, D3 states, the 82574 enters a link-disconnect state if it detects a link-disconnect condition on the Ethernet link. Note that the link-disconnect state is invisible to software (other than the Link Energy Detect bit state). In particular, while in D0 state, software might be able to access any of the device registers link-connect state ...
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PCIe Reference Clock PCIe PwrGd Reading EEPROM D3 write PHY Reset 1 PCIe Link L0 Wake Up Enabled PHY Power State full DState D0a Figure 21. D3hot Transition Timing Diagram Table 34. Notes to D3hot Timing Diagram Note 1 Writing ...
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Power Management and Delivery—82574 GbE Controller PCIe Reference Clock PCIe PwrGd Internal PCIe clock (2.5 GHz) Internal PwrGd (PLL) Reading EEPROM Reset to PHY (active low) D3 write 1 PCIe Link L0 Wake Up Enabled PHY Power State full DState ...
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Wake Up The 82574L supports two types of wake-up mechanisms: • Advanced Power Management (APM) wake up • PCIe power management wake up The PCIe power management wake up uses the PE_WAKE_N pin to wake the system up. The ...
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Power Management and Delivery—82574 GbE Controller 5.5.2 PCIe Power Management Wake Up The 82574L supports PCIe power management based wake ups. It can generate system wake-up events from three sources: • Reception of a Magic Packet*. • Reception of a ...
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Pre-Defined Filters The following packets are supported by the 82574's pre-defined filters: • Directed packet (including exact, multicast indexed, and broadcast) • Magic Packet* 1 • ARP /IPv4 request packet • Directed IPv4 packet • Directed IPv6 packet Each ...
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Power Management and Delivery—82574 GbE Controller 5.5.3.1.4 Magic Packet* Once the 82574 has been put into the Magic Packet* mode, it scans all incoming frames addressed to the node for a specific data sequence, which indicates to the controller that ...
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... Address Table (IP4AT). A successfully matched packet must contain a broadcast MAC address, a protocol type of 0x0806, an ARP opcode of 0x01, and one of the four programmed IPv4 addresses. The 82574L also handles ARP request packets that have VLAN tagging on both Ethernet II and Ethernet SNAP types Offset ...
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... WUFC. One IPv6 address is supported and is programmed in the IPv6 Address Table (IP6AT). A successfully matched packet must contain the station's MAC address, a protocol type of 0x0800, and the programmed IPv6 address. The 82574L also handles directed IPv6 packets that have VLAN tagging on both Ethernet II and Ethernet SNAP types ...
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Offset Bytes 5.5.3.2 Flexible Filter The 82574L supports four flexible filters for host wake up and two flexible filters for TCO wake up. For more details refer to ...
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Power Management and Delivery—82574 GbE Controller # of Offset bytes 5.5.3.2.2 Directed IPX Packet A valid directed IPX packet contains: • The station's MAC address. • A protocol type of 0x8137. • an IPX ...
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... Note: The NVM image must fit the specific NVM part being used. Special attention should be paid to NVM words and fields that vary, like the examples of NVMTYPE or NVSIZE. For the latest 82574L NVM images, contact your Intel representative. 6.1 Basic Configuration Table Table 36 lists the NVM map for the 0x00-0x3F address range ...
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Non-Volatile Memory (NVM) Map—82574 GbE Controller Word Used By 0x0F HW 0x10 HW 0x11 HW 0x12 HW 0x13 HW 0x14 HW 0x15 HW 0x16 HW 0x17 HW 0x18 HW 0x19 HW 0x1A HW 0x1B HW 0x1C HW 0x1D HW 0x1E ...
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... Network Interface Card (NIC), and thus unique for each copy of the NVM image. The first three bytes are vendor specific - for example, the IA is equal to [00 AA 00] or [00 A0 C9] for Intel products. The value from this field is loaded into the Receive Address Register 0 (RAL0/RAH0). ...
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Non-Volatile Memory (NVM) Map—82574 GbE Controller 6.1.1.3 Subsystem ID (Word 0x0B) If the load subsystem IDs in word 0x0A is set, this word is loaded to initialize the subsystem ID. The default value is 0x0. 6.1.1.4 Subsystem Vendor ID (Word ...
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Hardware Bit Name Default 1 11:8 NVSIZE 0x0 7 Reserved 0b 6 Reserved 1b 5 Reserved 0b 4 Reserved 1b 3 Reserved 1b 2 Reserved 0b 1 Reserved 0b 0 Reserved 0b 1. 0x09 for Flash. 6.1.1.7 NVM Protected Word ...
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Non-Volatile Memory (NVM) Map—82574 GbE Controller 6.1.1.8 NVM Protected Word 1 - NVP1 (Word 0x11) Hardware Bit Name Default 15:8 FSECER 0x20 7:1 Reserved 0x00 RAM_PWR_ 0 1b SAVE_EN 6.1.1.9 NVM Protected Word 2 - NVP2 (Word 0x12) Hardware Bit ...
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Extended Configuration Word 2 (Word 0x15) Hardware Bit Name Default 15:8 Reserved 0x0 7 Reserved 1b 6 Reserved 1b 5 Reserved 0b 4 Reserved 0b 3 Reserved 1b 2 Reserved 0b 1 Reserved 0b 0 Reserved 0b 6.1.1.12 Extended ...
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Non-Volatile Memory (NVM) Map—82574 GbE Controller 6.1.1.14 PCIe Init Configuration 1 Word (Word 0x18) Hardware Bit Name Default 15 Reserved 0b 14:12 L1_Act_Ext_Latency 0x6 (32 s-64 s) 11:9 L1_Act_Acc_Latency 0x6 (32 s-64 s) 8:6 L0s_Acc_Latency 0x3 (512 ns) 5:3 L0s_Se_Ext_Latency ...
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... However, in some applications, it might be necessary to change this value as explained in the Intel® 82574 Family Gigabit Ethernet Controller Specification Update. Please refer to Erratum #20 for more details. When set, the 82574 uses the PCIe reference clock supplied on 1b the connector (for add-in solutions) ...
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Non-Volatile Memory (NVM) Map—82574 GbE Controller 6.1.1.17 PCIe Control (Word 0x1B) Hardware Bit Name Default 1:0 Latency_To_Enter_L1 0x3 2 Electrical IDLE 0b 3 Reserved 0b 4 Skip Disable Disable 0b 6 Reserved 0b 9:7 MSI_X_NUM 0x4 10 ...
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LED 1 Configuration Defaults/PHY Configuration (Word 0x1C) Hardware Bit Name Default 3:0 LED1 Mode 0x4 4 Reserved 0b LED1 Blink 5 0b Mode 6 LED1 Invert 0b 7 LED1 Blink 1b 8 Reserved 1b 9 D0LPLU 0b 10 LPLU ...
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Non-Volatile Memory (NVM) Map—82574 GbE Controller 6.1.1.19 Reserved (Word 0x1D) Hardware Bit Name Default 15:9 Reserved 0x0 8 Reserved 1b 7 Reserved 0b 6 Reserved 0b 5 Reserved 0b 4:0 Reserved 0x0 6.1.1.20 Device Rev ID (Word 0x1E) Hardware Bit ...
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LED 0-2 Configuration Defaults (Word 0x1F) Hardware Bit Name Default Setting LED0 3:0 0x6 0x6 Mode 4 Reserved 0b 0b LED0 1 5 Blink 0b 0b Mode LED0 Invert LED0 Blink LED2 11:8 ...
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Non-Volatile Memory (NVM) Map—82574 GbE Controller 6.1.1.22 Flash Parameters - FLPAR (Word 0x20) Hardware Bit Name Default 15:8 FDEVER 0x60 7:6 Reserved 0x0 5 FLSSTn 0b 4 LONGC 0b 3:0 Reserved 0x0 6.1.1.23 Flash LAN Address - FLANADD (Word 0x21) ...
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LAN Power Consumption (Word 0x22) Hardware Bit Name Default LAN D0 15:8 0xF Power 7:5 Reserved 0x0 LAN D3 4:0 0x4 Power 6.1.1.25 Flash Software Detection Word (Word 0x23) The setting of this word to 0xFFFF enables detection of ...
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Non-Volatile Memory (NVM) Map—82574 GbE Controller 6.1.1.26 Initialization Control 3 (Word 0x24) Hardware Bit Name Default 15 Reserved 0b 14 Reserved 1b 13 Reserved 1b 12 Reserved 0b 11 Reserved 1b 10 APM Enable 0b 9 Reserved 0b 8 Reserved ...
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... PBA Number (Word 0x08 and 0x09) The nine-digit Printed Board Assembly (PBA) number used for Intel manufactured Network Interface Cards (NICs) is stored in the EEPROM. Note that through the course of hardware ECOs, the suffix field is incremented. The purpose of this information is to enable customer support (or any user) to identify the revision level of a product ...
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... The boot agent software configuration is controlled by the NVM with the main setup options stored in word 0x30. These options are those that can be changed by using the Control-S setup menu or by using the IBA Intel Boot Agent utility. Note that these settings only apply to Boot Agent software. ...
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Table 23. Boot Agent Main Setup Options Hardware Bit Name Default 15:13 Reserved 12 FDP 11:10 FSP 9 Reserved 8 DSM 1b 7 Reserved 4:3 DBS 2 Reserved 1:0 PS 120 82574 GbE Controller—Non-Volatile Memory (NVM) Map NVM ...
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... Word 0x31 contains settings that can be programmed by an OEM or network administrator to customize the operation of the software. These settings cannot be changed from within the Control-S setup menu or the IBA Intel Boot Agent utility. The lower byte contains settings that would typically be configured by a network administrator using the Intel Boot Agent utility ...
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Bit Name 4 DLWS 3 DBS 2 DPS 1 DTM 0 DSM 6.1.2.3.3 Boot Agent Configuration Customization Options (Word 0x32) Word 0x32 is used to store the version of the boot agent that is stored in the Flash image. When ...
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Non-Volatile Memory (NVM) Map—82574 GbE Controller 6.1.2.3.4 IBA Capabilities (Word 0x33) Word 0x33 is used to enumerate the boot technologies that have been programmed into the Flash updated by IBA configuration tools and is not updated or read ...
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Checksum Word Calculation (Word 0x3F) The checksum word (0x3F) is used to ensure that the base NVM image is a valid image. The value of this word should be calculated such that after adding all the words (0x00- 0x3F), ...
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Non-Volatile Memory (NVM) Map—82574 GbE Controller 6.2.1.3 APT SMBus Control (Word 0x27) Hardware Bit Name Default SMBus 15:8 Fragment 0x20 0x20 Size Notification 7:0 0x0 0xFF Timeout 6.2.1.4 APT Init Flags (Word 0x28) Hardware Bit Name Default 15:6 Reserved 5 ...
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APT Code Pointer (Word 0x2A) Hardware Bit Name Default 15:12 Reserved 11:0 Pointer 1. Code in the NVM is organized such that the lower word of a Dword code, is stored first. Note: APT code size and pointer should ...
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Non-Volatile Memory (NVM) Map—82574 GbE Controller 6.2.2.3 NC-SI Management Configuration (Word 0x2D) Hardware Bit Name Default 15:14 Reserved 13:4 Code Size 3:2 Reserved 1:0 RAM Partitioning 6.2.2.4 NC-SI Configuration (Word 0x2E) Hardware Bit Name Default 15 Reserved 14:12 Package ID ...
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Inline Functions 7.1 Packet Reception Packet reception consists of recognizing the presence of a packet on the wire, performing address filtering, storing the packet in the receive data FIFO, transferring the data to one of the two receive queues ...
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Inline Functions—82574 GbE Controller Good packets are defined as those packets with no: • CRC error • Symbol error • Sequence error • Length error • Alignment error • Where carrier extension or RX_ERR errors are detected. However, if the ...
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... For standard 802.3 packets (non-VLAN) the packet checksum is by default computed over the entire packet from the first byte of the DA through the last byte of the CRC, including the Ethernet and IP headers. Software can modify the starting offset for the packet checksum calculation via the Receive Checksum Control register (RXCSUM). ...
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Inline Functions—82574 GbE Controller TCPCS (bit 5) - TCP checksum calculated on packet UDPCS (bit 4) - UDP checksum calculated on packet VP (bit 3) - Packet is 802.1q (matched VET) Reserved (bit 2) - Reserved EOP (bit 1) - ...
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TCPE (bit 5) - TCP/UDP checksum error CXE (bit 4) - Carrier extension error Rsv (bit 3) - Reserved SEQ (bit 2) - Sequence error SE (bit 1) - Symbol error CE (bit 0) - CRC error or alignment error ...
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Inline Functions—82574 GbE Controller 7.1.4.1 Buffer Address (64-Bit, Offset 0.0) The field contains the physical address of the receive data buffer. The size of the buffer is defined by the RCTL register (RCTL.BSIZE, RCTL.BSEX, RCTL.DTYP and RCTL. FLXBUF fields). 7.1.4.2 ...
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... For standard 802.3 packets (non-VLAN) the packet checksum is by default computed over the entire packet from the first byte of the DA through the last byte of the CRC, including the Ethernet and IP headers. Software can modify the starting offset for the packet checksum calculation via the Receive Checksum Control register (RXCSUM). ...
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Inline Functions—82574 GbE Controller UDPV (bit 10) - Valid UDP XSUM IPIDV (bit identification valid TST (bit 8) - Time stamp taken Rsvd (bit 7) - Reserved IPCS (bit 6) IPv4 checksum calculated on packet - same ...
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ACK (bit 15): The ACK bit indicates that the received packet was an ACK packet with or without TCP payload depending on the RFCTL.ACKD_DIS bit. PKTTYPE (bit 19:16): The PKTTYPE field defines the type of the packet that was detected ...
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Inline Functions—82574 GbE Controller CE (bit 4) - CRC error or alignment error - Same as legacy descriptor. Reserved (bits 7, 3:0) - Reserved RXE IPE TCPE CXE SEQ SE CE: Same as legacy descriptor. Length (16-bit, offset 8.32): Same ...
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Packet Split Receive Descriptor The 82574L uses the packet split feature when the RFCTL.EXSTEN bit is set and RCTL.DTYP=01b. The software device driver must also program the buffer sizes in the PSRCTL register. Descriptor Read Format ...
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Inline Functions—82574 GbE Controller Descriptor Write-Back Format Packet Checksum 8 VLAN Tag 1 Length Note: Light-blue fields are mutually exclusive by RXCSUM.PCSD MRQ - Same as extended Rx descriptor. Packet Checksum, IP Identification, RSS ...
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HLEN (bit 9:0): The HLEN field indicates the header length in byte count that was analyzed by the 82574. The 82574L posts the first HLEN bytes of the incoming packet to buffer zero of the Rx descriptor. Packet types supported ...
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Inline Functions—82574 GbE Controller 7.1.6 Receive Descriptor Fetching The fetching algorithm attempts to make the best use of PCIe bandwidth by fetching a cache-line (or more) descriptor with each burst. The following paragraphs briefly describe the descriptor fetch algorithm and ...
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Null Descriptor Padding Hardware stores no data in descriptors with a null data address. Software can make use of this property to cause the first condition under receive descriptor packing to occur early. Hardware writes back null descriptors with ...
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Inline Functions—82574 GbE Controller The receive descriptor head and tail pointers reference 16-byte blocks of memory. Shaded boxes in the figure represent descriptors that have stored incoming packets but have not yet been recognized by software. Software can determine if ...
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Receive Interrupts The following indicates the presence of new packets: • Receive Timer (ICR.RXT0) due to packet delay timer (RDTR) A predetermined amount of time has elapsed since the last packet was received and transferred to host memory. Every ...
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Inline Functions—82574 GbE Controller Initial State DISABLED other receive interrupts INT GENERATED Figure 31. Packet Delay Timer Operation (With State Diagram) Figure 32 shows how the packet timer and absolute timer can be used together: packet received & xferred to ...
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C ase A: U sing only an absolute tim er PKT #1 C ase B: U sing an absolute tim e in conjunction w ith the P acket tim er A bsolute Tim er Value PKT #1 PKT #2 1) ...
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... VLAN striping is not enabled by the CTRL.VME. If VLAN header strip is enabled, the packet checksum and the starting offset of the packet checksum exclude the VLAN header due to masking of VLAN header. For example, for an Ethernet II frame encapsulated as an 802.3ac VLAN packet and CTRL.VME is set and with RXCSUM.PCSS set to 14, the packet checksum would include the entire encapsulated frame, excluding the 14-byte Ethernet header (DA, SA, Type/Length) and the 4-byte q-tag ...
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... SNAP/VLAN Filter This filter checks the next headers looking for an IP header capable of decoding Ethernet II, Ethernet SNAP, and IEEE 802.3ac headers. It skips past any of these intermediate headers and looks for the IP header. The receive configuration settings determine which next headers are accepted. See the various receive control configuration registers such as RCTL (RCTL ...
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Inline Functions—82574 GbE Controller 7.1.10.3 IPv4 Filter This filter checks for valid IPv4 headers. The version field is checked for a correct value (4). IPv4 headers are accepted if they are any size greater than or equal to 5 (Dwords). ...
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However, RSS is the only usage that is described specifically. Other uses should make use of the available hardware. Multiple receive queues are enabled when the RXCSUM.PCSD bit is set (packet checksum is disabled) and the Multiple Receive Queues Enable ...
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Inline Functions—82574 GbE Controller Parsed receive packet RSS Hash 32 Packet descriptor MRQ disables or (RSS & not decodeable) Figure 33. RSS Block Diagram 7.1.11.1 RSS Hash Function The 82574L’s hash function follows Microsoft’s* definition. A single hash function is ...
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IPv6Ex - The 82574L parses the packet to identify an IPv6 packet. Extension headers should be parsed for a Home-Address-Option field (for source address) or the Routing-Header-Type-2 field (for destination address). Note that the packet is not required to ...
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Inline Functions—82574 GbE Controller IPv6 hash types: • S2a - TcpIPv6 is enabled as defined above, or • S2b - TcpIPv6, IPv6Ex, and IPv6 are enabled - the packet is first parsed according to TcpIPv6 rules. If not identified as ...
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The following four pseudo-code examples are intended to help clarify exactly how the hash performed in four cases, IPv4 with and without ability to parse the TCP header, and IPv6 with an without a TCP header. 7.1.11.1.1 ...
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Inline Functions—82574 GbE Controller 7.1.11.3 RSS Verification Suite Assume that the random key byte-stream is: 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4, 0x77, ...
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... While the packet is passing through the DMA and MAC units, relevant off load functions are incorporated according to the commands in the descriptors. 10 After the entire packet is fetched by the hardware it is transmitted to the Ethernet link. After a DMA of each buffer is complete, if the RS bit in the command byte is set, the DMA updates the 11 Status field of the appropriate descriptor and writes back the descriptor to the descriptor ring in host memory ...
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Inline Functions—82574 GbE Controller • Software places the rest of the data to be transmitted in the host memory indicated to the hardware by additional data descriptors. • Hardware splits the data into multiple packets according to the Maximum Segment ...
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Descriptors between the head and the tail pointers are descriptors that have been prepared by software and are owned by hardware. 7.2.4.1 Transmit Descriptor Fetching The descriptor processing strategy for transmit descriptors is essentially the same as for receive descriptors. ...
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Inline Functions—82574 GbE Controller 7.2.4.3 Determining Completed Frames as Done Software can determine if a packet has been sent by the following method: • Setting the RS bit in the transmit descriptor command field and checking the DD bit of ...
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The device automatically selects the appropriate mode to use based on the current packet transmission: legacy, extended, or segmentation. Note: While the architecture supports arbitrary ordering rules for the various descriptors, there are restrictions including: — Context descriptors should not ...
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Inline Functions—82574 GbE Controller 7.2.8 Transmit Interrupts Hardware supplies the transmit interrupts described below. These interrupts are initiated via the following conditions: • Transmit Descriptor Ring Empty (ICR.TXQE) - All descriptors have been processed. The head pointer is equal to ...
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Transmit Descriptor Formats The original descriptor is referred to as the legacy descriptor and is described in section 7.2.10.1. The two new descriptor types are collectively referred to as extended descriptors. One of the new descriptor types is quite ...
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Inline Functions—82574 GbE Controller 7.2.10.1.2 Length Length (TDESC.LENGTH) specifies the length in bytes to be fetched from the buffer address. The maximum length associated with any single legacy descriptor is 16288 bytes. Note: The maximum allowable packet size for transmits ...
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... Send generic Ethernet packet. IFCS controls insertion of FCS in normal Ethernet 0 packets. Send 802.1Q packet; the Ethernet Type field comes from the VET register and the 1 VLAN data comes from the special field of the TX descriptor; hardware appends the FCS/CRC - command should reflect by setting IFCS to 1b. ...
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Inline Functions—82574 GbE Controller When IC is set, hardware inserts a checksum value calculated from the CSS bit value to the CSE bit value the end of packet. The checksum value is inserted in the header at the ...
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VLAN Field The VLAN field is used to provide the 802.1Q/802.1ac tagging information. The VLAN field is ignored if the VLE bit the EOP bit is 0b PRI CFI 7.2.10.2 Context Transmit ...
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... The total length of each frame (or section) sent by the TCP segmentation mechanism (excluding 802.3ac tagging and Ethernet CRC) is MSS bytes + HRDLEN. The one exception is the last packet of a TCP segmentation that might be shorter. This field is ignored if TDESC.TSE is not set ...
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Header Length - HDRLEN HDRLEN is used to specify the length (in bytes) of the header to be used for each frame of a TCP segmentation operation. The first HDRLEN bytes fetched from data descriptor(s) are stored internally and ...
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Inline Functions—82574 GbE Controller IDE (bit 7) - Interrupt Delay Enable SNAP (bit 6) - SNAP DEXT (bit 5) - Descriptor extension (must be 1b for this descriptor type) Rsv (bit 4) - Reserved RS (bit 3) - Report status ...
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The TCP bit identifies the packet as either TCP or UDP (non-TCP). This affects the processing of the header information. 7.2.10.7 Status - STA Four bits are reserved to provide transmit status, although only one is currently assigned for this ...
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... RSV (bit 4) - Reserved RS (bit 3) - Report status TSE (bit 2) - TCP segmentation enable IFCS (bit 1) - Insert FCS (also controls insertion of Ethernet CRC) EOP (bit 0) - End of packet IDE activates a transmit interrupt delay timer. Hardware loads a countdown register when it writes back a transmit descriptor that has RS and IDE set. The value loaded comes from the IDV field of the Interrupt Delay (TIDV) register ...
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... TSE indicates that this descriptor is part of the current TCP segmentation context. If this bit is not set, the descriptor is part of the normal non-segmentation context. IFCS controls insertion of the Ethernet CRC. The packet FCS covers the TCP/IP headers. Therefore, when using the TCP segmentation offload, software must also use the FCS insertion ...
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Inline Functions—82574 GbE Controller 7.2.11.4 Status - STA The status field is written back to host memory in cases where the RS bit is set in the command field. The DD bit indicates that the descriptor is done after the ...
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... The stack does not need to partition the block to fit the MTU size, saving CPU cycles. • The stack only computes one Ethernet, IP, and TCP header per segment (entire packet), saving CPU cycles. • The stack interfaces with the software device driver only once per block transfer, instead of once per frame. • ...
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... Ethernet Figure 39. TCP/IP Packet Format Frame formats supported by the 82574 include: • Ethernet 802.3 • IEEE 802.1q VLAN (Ethernet 802.3ac) • Ethernet Type 2 • Ethernet SNAP • IPv4 headers with options • IPv6 headers with IP option next headers • TCP with options • ...
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... Once the TCP segmentation context has been set, the next descriptor (data descriptor) provides the initial data to transfer. This first data descriptor must point to data containing an Ethernet header of the type indicated. The 82574L fetches the prototype (partial pseudo-header) header from the host data buffer into an internal buffer and this header is prepended to every packet for this TSO operation ...
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Inline Functions—82574 GbE Controller 7.3.6 TCP Segmentation Use of Multiple Data Descriptors TCP segmentation enables a series of data descriptors, each referencing a single physical address page, to reference a large packet contained in a single virtual-address buffer. The only ...
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IP/TCP/UDP Header Updating IP/TCP/UDP header is updated for each outgoing frame based on the IP/TCP header prototype (partial pseudo-header) which the hardware gets from the first descriptor(s) and stores on chip. The IP/TCP/UDP headers are fetched from host memory ...
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Inline Functions—82574 GbE Controller IPv4 Header • IP Identification: incremented from last value (wrap around) • IP Total Length = MSS + HDRLEN - IPCSS • IP Checksum IPv6 Header • Payload Length = MSS + HDRLEN - IPCSS - ...
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UDP Header • UDP length: (last frame payload bytes + HDRLEN) - TUCSS • UDP Checksum 7.4 Interrupts The 82574L supports the following interrupt modes: • PCI legacy interrupts • PCI MSI - Message Signaled Interrupts • PCI MSI-X - ...
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Inline Functions—82574 GbE Controller The following configuration and parameters are involved: • The IVAR.INT_Alloc[4:0] entries map two Tx queues, two Rx queues and other events to 5 interrupt vectors • The ICR[24:20] bits reflect specific interrupt causes • Five MSI-X ...
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The interrupt causes include: • The receive and transmit related interrupts (including new per queue cause). • Other bits in this register are the legacy indication of interrupts as the MDIC complete, management and link status change. There is a ...
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Inline Functions—82574 GbE Controller 7.4.4 Interrupt Moderation The 82574L implements interrupt moderation to reduce the number of interrupts software processes. The moderation scheme is based on a timer called ITR Interrupt Throttle register). In general terms, the ITR defines an ...
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No Yes No No Figure 41. Interrupt Throttle Flow Diagram For cases where the 82574 is connected to a small number of clients desirable to fire off the interrupt as soon as possible with minimum latency. For these ...
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Inline Functions—82574 GbE Controller Case A: Heavy load, interrupts moderated Intr Pkt Pkt Case B: Light load, interrupts immediately on packet receive Intr Pkt 7.4.5 Clearing Interrupt Causes The 82574L has three methods available for to clear ICR bits: auto-clear, ...
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... Note: The CRC for the 802.1q tagged frame is re-computed, so that it covers the entire tagged frame including the 802.1q tag header. Also, maximum frame size for an 802.1q VLAN packet is 1522 octets as opposed to 1518 octets for a normal 802.3z Ethernet packet. 7.5.1.1 802.1q Tagged Frames For 802.1q, the Tag Header field consists of four octets comprised of the Tag Protocol Identifier (TPID) and Tag Control Information (TCI) ...
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... CTRL.VME bit is set to 1b, and the incoming packet is an 802.1q VLAN packet (for example, it's Ethernet Type field matched the VET), then the 82574 strips the 4-byte VLAN tag from the packet, and stores the TCI in the Special field of the receive descriptor ...
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The Virtual LAN ID field indexes a 4096 bit vector. If the indexed bit in the vector is one; there is a virtual LAN match. Software might set the entire bit vector to ones if the node does not implement ...
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Inline Functions—82574 GbE Controller Each of the three LED's might be configured to use one of a variety of sources for output indication. The Mode bits control the LED source: • LINK_100/1000 is asserted when link is established at either ...
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The 1588 standard specifically addresses the needs of measurement and control systems: • Spatially localized • s to sub-s accuracy • Administration free • Accessible for both high-end devices and low-cost, low-end devices The time sync mechanism activation is possible ...
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Inline Functions—82574 GbE Controller T1 Timestamp Master T4 Timestamp Figure 42. Sync Flow and Offset Calculation The hardware responsibilities are: 1. Identify the packets that require time stamping. 2. Timestamp the packets on both Rx and Tx paths. 3. Store ...
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Table 45. Chronological Order of Events for Sync and Path Delay Generate a sync packet with timestamp notification in descriptor. Timestamp the packet and store the value in registers (T1). Timestamp incoming sync packet, store the value in register and ...
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Inline Functions—82574 GbE Controller 7.7.3.1 System Time Structure and Mode of Operation The time sync logic contains an up counter to maintain the system time value. This is a 64-bit counter that is built of the SYSTIML and SYSTIMH registers. ...
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On the Rx this logic parses the traversing frame and if Rx timestamp is enabled and it matches the Ethertype, UDP port (if needed), version and message type as defined in the register described in latched in the timestamp registers. ...
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Inline Functions—82574 GbE Controller After offset calculation the system time register should be updated. This is done by writing the calculated offset to TIMADJL and TIMADJH registers. The order should be as follows: 1. Write the lower portion of the ...
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... PTP Message Over Layer 2 Ethernet (L2) Table 48. PTP Message Over Layer 4 Ethernet (L2) When a PTP packet is recognized (by Ethertype or UDP port address) on the Rx side, the version should be checked V1, then the control field at offset 32 should be compared to control field in register described at at offset 0 (messageId) should be used for comparison to messageId field. ...
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Inline Functions—82574 GbE Controller Table 50. Message Decoding for V2 (MessageId Field at Offset 0) MessageId PTP_SYNC_MESSAGE PTP_DELAY_REQ_MESSAGE PTP_PATH_DELAY_REQ_MESSAGE PTP_PATH_DELAY_RESP_MESSAGE Unused PTP_FOLLOWUP_MESSAGE PTP_DELAY_RESP_MESSAGE PTP_PATH_DELAY_FOLLOWUP_MESSAGE PTP_ANNOUNCE_MESSAGE PTP_SIGNALLING_MESSAGE PTP_MANAGEMENT_MESSAGE Unused If V2 mode is configured in PTP_PATH_DELAY_REQ_MESSAGE and PTP_PATH_DELAY_RESP_MESSAGE for any value ...
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... Software-based management applications provide the ability to administer systems while the operating system is functioning in a normal power state (not in a pre-boot state or powered-down state). The Intel® System Management Bus (SMBus) Interface and the Network Controller - Sideband Interface (NC-SI) for fills the the 82574 management void that exists when the operating system is not running or fully functional ...
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... NC-SI specification) and the protocol layer is completely different. 8.4 SMBus Pass-Through Interface SMBus is the system management bus defined by Intel® Corporation in 1995 used in personal computers and servers for low-speed system management communications. The SMBus interface is one of two pass-through interfaces available in the 82574L. ...
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... General The SMBus sideband interface includes the standard SMBus commands used for assigning a slave address and gathering device information as well as Intel® proprietary commands used specifically for the pass-through interface. 8.4.2 Pass-Through Capabilities This section details the specific manageability capabilities the 82574L provides while in SMBus mode ...