WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 336

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.5.13
10.2.5.14
10.2.5.15
336
Setting this register to 0x0 disables the absolute timer mechanism (the RDTR register
should be used with a value of 0x0 to cause immediate interrupts for all receive
packets).
Receive interrupts due to a Receive Packet Timer (RDTR) expiration cancels a pending
RADV interrupt. If enabled, the RADV count-down timer is reloaded but halted, so as to
avoid generation of a serious second interrupt after the RDTR has been noted.
Receive Small Packet Detect Interrupt- RSRPD (0x02C00; R/W)
Receive ACK Interrupt Delay Register - RAID (0x02C08; RW)
If an immediate (non-scheduled) interrupt is desired for any received ACK frame, the
ACK_DELAY should be set to x00.
Receive Checksum Control - RXCSUM (0x05000; RW)
The Receive Checksum Control register controls the receive checksum offloading
features of the 82574. The 82574L supports the offloading of three receive checksum
calculations: the packet checksum, the IP header checksum, and the TCP/UDP
checksum.
SIZE
Reserved
RSV
ACK_DELAY
PCSS
IPOFLD
TUOFLD
Reserved
CRCOFL
IPPCSE
PCSD
Reserved
Field
Field
Field
11:0
31:12
16:31
15:0
7:0
8
9
10
11
12
13
31:14
Bit(s)
Bit(s)
Bit(s)
0x0
X
0x0
0x0
0x0
1b
1b
0b
0b
0b
0b
0x0
Initial
Initial
Initial
Value
Value
Value
If the interrupt is enabled any received packet of size <= SIZE asserts
an interrupt. SIZE is specified in bytes and includes the headers and
the CRC. It does not include the VLAN header in size calculation if it is
stripped.
Reserved.
Reserved
ACK delay timer measured in increments of 1.024 s. When the
receive ACK frame detect interrupt is enabled in the IMS register, ACK
packets being received uses a unique delay timer to generate an
interrupt. When an ACK is received, an absolute timer loads to the
value of ACK_DELAY. The interrupt signal is set only when the timer
expires. If another ACK packet is received while the timer is counting
down, the timer is not reloaded to ACK_DELAY.
Packet Checksum Start
IP Checksum Offload Enable
TCP/UDP Checksum Offload Enable
Reserved
CRC32 Offload Enable
IP Payload Checksum Enable
Packet Checksum Disable
Reserved
82574 GbE Controller—Driver Programing Interface
Description
Description
Description