WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 346

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
10.2.6.3
Note:
10.2.6.4
346
This register controls the Inter Packet Gap (IPG) timer. IPGT specifies the IPG length for
back-to-back transmissions. IPGR1 contains the length of the first part of the IPG time
for non back-to-back transmissions. During this time, the IPG counter restarts if any
carrier sense event occurs. Once the time specified by IPGR1 has elapsed, carrier sense
does not affect the IPG counter. IPGR2 specifies the total IPG time for non back-to-back
transmissions. According to the IEEE 802.3 spec, IPGR1 should be 2/3 of IPGR2. IPGR1
and IPGR2 are significant only for half-duplex operation.
The actual time waited for IPGT and IPGR2 is 6 MAC clocks (48 ns @ 1 Gb/s) longer
than the value programmed in the register. This is due to the implementation of the
asynchronous interface between the internal DMA and MAC engines. Therefore, the
suggested value that software should program into this register is 0x00602006. This
corresponds to: IPGT = 6 (6+6 = total delay of 12); IPGR1 = 8; and IPGR2 = 6 (6+6 =
total delay of 12). Also, it should be noted that this six MAC clock delay is longer than
implementations. For previous implementations, the actual time waited for any of the
IPG timers was two MAC clocks (16 ns) longer than the value programmed in the
register. Thus, for previous implementations, the suggested value for software to
program this register was 0x00A00200A.
Adaptive IFS Throttle - AIT (0x00458; RW)
Adaptive IFS throttles back-to-back transmissions in the transmit packet buffer and
delays their transfer to the CSMA/CD transmit function, and thus can be used to delay
the transmission of back-to-back packets on the wire. Normally, this register should be
set to zero. However, if additional delay is desired between back-to-back transmits,
then this register can be set with a value greater than zero.
The Adaptive IFS field provides a similar function to the IPGT field in the TIPG register
(see
transmission timing.
If the value of the Adaptive IFS field is less than the IPG Transmit Time field in the
Transmit IPG registers then it has no effect, as the chip selects the maximum of the two
values.
Transmit Descriptor Base Address Low - TDBAL (0x03800 +
n*0x100[n=0..1]; RW)
Reserved
AIFS
Reserved
0
TDBAL
Field
Field
Field
Section
10.2.6.2). However, it only affects the initial transmission timing, not re-
31:30
15:0
31:16
3:0
31:4
Bit(s)
Bit(s)
Bit(s)
0x0
0x0000
0x0000
0x0
X
Initial
Initial
Initial
Value
Value
Value
Reserved
Reads as 0b. Should be written to 0b for future compatibility.
Adaptive IFS Value
This value is in units of 8 ns.
This field should be written with 0x0.
Ignored on writes. Returns 0x0 on reads.
Transmit Descriptor Base Address Low
82574 GbE Controller—Driver Programing Interface
Description
Description
Description