WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 3

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet—82574 GbE Controller
Contents
1.0
2.0
3.0
Introduction ............................................................................................................ 12
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Pin Interface ........................................................................................................... 20
2.1
2.2
2.3
2.4
Interconnects .......................................................................................................... 28
3.1
3.2
3.3
Scope .............................................................................................................. 12
Number Conventions ......................................................................................... 12
Acronyms......................................................................................................... 13
Reference Documents ........................................................................................ 14
82574 Architecture Block Diagram ....................................................................... 15
System Interface............................................................................................... 15
Features Summary ............................................................................................ 15
Product Codes................................................................................................... 18
Pin Assignments................................................................................................ 20
Pull-Up/Pull-Down Resistors and Strapping Options ................................................ 21
Signal Type Definition ........................................................................................ 21
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
Package ........................................................................................................... 27
PCIe ................................................................................................................ 28
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
Ethernet Interface ............................................................................................. 43
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
SPI Non-Volatile Memory Interface ...................................................................... 53
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
PCIe ..................................................................................................... 21
NVM Port............................................................................................... 22
System Management Bus (SMBus) Interface .............................................. 23
NC-SI and Testability .............................................................................. 23
LEDs .................................................................................................... 24
PHY Pins ............................................................................................... 24
Miscellaneous Pin ................................................................................... 25
Power Supplies and Support Pins .............................................................. 26
Architecture, Transaction, and Link Layer Properties ................................... 29
General Functionality .............................................................................. 30
Transaction Layer................................................................................... 30
Flow Control .......................................................................................... 35
Host I/F ................................................................................................ 37
Error Events and Error Reporting .............................................................. 38
Link Layer ............................................................................................. 41
PHY ...................................................................................................... 42
Performance Monitoring .......................................................................... 43
MAC/PHY GMII/MII Interface ................................................................... 43
Duplex Operation for Copper PHY/GMII/MII Operation ................................. 44
Auto-Negotiation & Link Setup Features .................................................... 45
Loss of Signal/Link Status Indication ......................................................... 48
10/100 Mb/s Specific Performance Enhancements....................................... 49
Flow Control .......................................................................................... 50
General Overview................................................................................... 53
Supported NVM Devices .......................................................................... 53
NVM Device Detection ............................................................................. 54
Device Operation with an External EEPROM................................................ 55
Device Operation with Flash..................................................................... 55
Shadow RAM ......................................................................................... 55
NVM Clients and Interfaces ...................................................................... 57
NVM Write and Erase Sequence................................................................ 58
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