WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 92

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 21.
Table 34.
5.4.5.2
92
Wake Up Enabled
D3hot Transition Timing Diagram
Notes to D3hot Timing Diagram
Transition From D0a to D3 and Back with PE_RST_N
Figure 22
Reading EEPROM
PHY Power State
1
2
3
4
5
6
7
Note
PCIe Reference
PCIe PwrGd
PHY Reset
PCIe Link
DState
Clock
Writing 11b to the Power State field of the PMCSR transitions the 82574 to D3.
The system keeps the 82574 in D3 state for an arbitrary amount of time.
To exit D3 state the system writes 00b to the Power State field of the PMCSR.
APM wake up or SMBus mode can be enabled based on what is read in the NVM.
After reading the NVM, reset to the PHY is de-asserted. The PHY operates at reduced-speed if APM
wake up or SMBus is enabled, else powered-down.
The system can delay an arbitrary time before enabling memory access.
Writing a 1b to the Memory Access Enable bit or to the I/O Access Enable bit in the PCI Command
register transitions the 82574 from D0u to D0 state and returns the PHY to full-power/speed
operation.
shows the 82574’s reaction to a D3 transition.
D0a
D3 write
L0
full
1
Any mode
2
82574 GbE Controller—Power Management and Delivery
D3
power-managed
L1
Description
D0 Write
3
Read
Auto
t
ee
5
Conf.
Ext.
4
t
d0me
m
managed
D0u
power-
APM / SMBus
6
Memory Access Enable
L0
7
full
D0