WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 89

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Management and Delivery—82574 GbE Controller
5.4.4.2.3
Entry to D3 State
Transition to the D3 state is through a configuration write to the Power State field of the
PCI-PM registers.
Prior to transition from D0 to the D3 state, the software device driver disables
scheduling of further tasks to the 82574, as follows:
If wake-up capability is needed, the software device driver should set up the
appropriate wake-up registers and the system should write a 1b to the PME_En bit in
the PMCSR or to the AUX Power PM Enable bit of the PCIe Device Control register prior
to the transition to D3.
As a response to being programmed into the D3 state, the 82574 brings its PCIe link
into the L1 link state. As part of the transition into L1 state, the 82574 suspends
scheduling of new Transaction Layer Protocols (TLPs) and waits for the completion of all
previous TLPs it has sent. The 82574L clears the Memory Access Enable and I/O Access
Enable bits of the PCI Command register, which disables memory access decode. Any
receive packets that have not been transferred into system memory are kept in the
device (and discarded later on D3 exit). Any transmit packets that were not sent, can
still be transmitted (assuming the Ethernet link is up).
To reduce power consumption, if any of ASF manageability, APM wake, and PCI-PM PME
is enabled, the PHY auto-negotiates to a lower link speed on D3 entry (see
Section
• It masks all interrupts
• It does not write to the Transmit Descriptor Tail (TDT) register
• It does not write to the Receive Descriptor Tail (RDT) register
• Operates the master disable algorithm as defined in
5.4.4.2.3).
Section
3.1.3.10.
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