WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 169

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inline Functions—82574 GbE Controller
Note:
Note:
Note:
IDE (bit 7) - Interrupt Delay Enable
SNAP (bit 6) - SNAP
DEXT (bit 5) - Descriptor extension (must be 1b for this descriptor type)
Rsv (bit 4) - Reserved
RS (bit 3) - Report status
TSE (bit 2) - TCP segmentation enable
IP (bit 1) - IP Packet type (IPv4=1b, IPv6=0b)
TCP (bit 0) - Packet type (TCP=1b,UDP=0b)
IDE activates a transmit interrupt delay timer. Hardware loads a countdown register
when it writes back a transmit descriptor that has RS and IDE set. The value loaded
comes from the IDV field of the Interrupt Delay (TIDV) register. When the count
reaches zero, a transmit interrupt occurs if transmit descriptor write-back interrupts
(TXDW) are enabled. Hardware always loads the transmit interrupt counter whenever it
processes a descriptor with IDE set even if it is already counting down due to a
previous descriptor. If hardware encounters a descriptor that has RS set, but not IDE, it
generates an interrupt immediately after writing back the descriptor and clears the
interrupt delay timer. Setting the IDE bit has no meaning without setting the RS bit.
Although the transmit interrupt may be delayed, the descriptor write-back requested
by setting the RS bit is performed without delay unless descriptor write-back bursting is
enabled.
SNAP indicates that the TCP segmentation MAC header includes a SNAP header that
needs to be updated by hardware.
The DEXT bit identifies this descriptor as one of the extended descriptor types and
must be set to 1b.
When the RS bit is set, hardware writes back the DD bit once the DMA fetch completes.
Descriptors with the null address (0), or zero length, transfer no data. If they have the
RS bit in the command byte set, then the DD field in the status word is written when
hardware processes them. Hardware only sets the DD bit for descriptors with RS set.
Software can set the RS bit in each descriptor or, more likely, in specific descriptors
such as the last descriptor of each packet.
TSE indicates that this descriptor is setting the TCP segmentation context. If this bit is
zero, the descriptor defines a single packet TCP/UDP, IP checksum offload mode. When
a descriptor of this type is processed, the device immediately updates the mode in
question (TCP segmentation or checksum offloading) with values from the descriptor.
This means that if any normal packets or TCP segmentation packets are in progress (a
descriptor with EOP set has not been received for the given context) the results will
likely be undesirable.
The IP bit is used to indicate what type of IP (IPv4 or IPv6) packet is used in the
segmentation process. This is necessary for the 82574 to know where the IP Payload
Length field is located. This does not override the checksum insertion bit, IXSM. The IP
bit must only be set for IPv4 packets and cleared for IPv6 packets.
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