WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 303

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
Note:
For an MDI read cycle the sequence of events is as follows:
For an MDI write cycle, the sequence of events is as follows:
An MDI read or write might take as long as 64 s from the CPU write to the Ready bit
assertion.
If an invalid op-code is written by software, the MAC does not execute any accesses to
the PHY registers.
If the PHY does not generate a zero as the second bit of the turn-around cycle for
reads, the MAC aborts the access, sets the E (error) bit, writes 0xFFFF to the data field
to indicate an error condition, and sets the Ready bit.
1. The CPU performs a PCIe write cycle to the MII register with:
2. The MAC applies the following sequence on the MDIO signal to the PHY:
3. The PHY returns the following sequence on the MDIO signal: <0><DATA><IDLE>.
4. The MAC discards the leading bit and places the following 16 data bits in the MII
5. The 82574L asserts an interrupt indicating MDI done if the Interrupt Enable bit was
6. The 82574L sets the Ready bit in the MII register indicating the read is complete.
7. The CPU might read the data from the MII register and issue a new MDI command.
1. The CPU performs a PCIe write cycle to the MII register with:
2. The MAC applies the following sequence on the MDIO signal to the PHY:
3. The 82574L asserts an interrupt indicating MDI done if the Interrupt Enable bit was
4. The 82574L sets the Ready bit in the MII register to indicate step 2 has been
5. The CPU might issue a new MDI command.
a. Ready = 0b.
b. Interrupt Enable bit set to 1b or 0b.
c.
d. PHYADD = PHY address from the MDI register.
e. REGADD = Register address of the specific register to be accessed (0 through
<PREAMBLE><01><10><PHYADD><REGADD><Z> where the Z stands for the
MAC tri-stating the MDIO signal.
register.
set.
a. Ready = 0b.
b. Interrupt Enable bit set to 1b or 0b.
c.
d. PHYADD = PHY address from the MDI register.
e. REGADD = Register address of the specific register to be accessed (0 through
f.
<PREAMBLE><01><01><PHYADD><REGADD><10><DATA><IDLE>.
set.
completed.
Op-Code = 10b (read).
31).
Op-Code = 01b (write).
31).
Data = Specific data for desired control of the PHY.
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