WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 367

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
10.2.8
10.2.8.1
Management Register Descriptions
Wake Up Control Register - WUC (0x05800; RW)
The PME_En and PME_Status bits are reset when Internal Power On Reset is 0b. When
D3 cold is not supported, these bits are also reset by the de-assertion (rising edge) of
PCI_RST_N. The other bits are reset on the standard internal resets. See
for details.
APME
PME_En
PME_Status
APMPME
LSCWE
LSCWO
FTFA1
FTF1_EN
FTFA0
FTF0_EN
Reserved
Field
0
1
2
3
4
5
6
7
8
9
31:8
Bit(s)
0b
0b
0b
0b
0b
0b
0b
0b
0
0
0b
Initial
Value
Advance Power Management Enable
If 1b, APM Wakeup is enabled (see
This bit is loaded from NVM.
PME_En
This read/write bit is used by the software device driver to access the
PME_En bit of the Power Management Control / Status Register
(PMCSR) without writing to PCIe configuration space.
PME_Status
This bit is set when the 82574 receives a wake-up event. It is the
same as the PME_Status bit in the PMCSR. Writing a 1b to this bit
clears the PME_Status bit in the PMCSR.
Assert PME On APM Wakeup
If set to 1b, the 82574 sets the PME_Status bit in the PMCSR and
asserts PE_WAKE_N when APM Wake Up is enabled and the 82574
receives a matching magic packetsee
Link Status Change Wake Enable
Enables wake on link status change as part of APM wake capabilities.
Link Status Change Wake Override
If set to 1b, wake on link status change does not depend on the LNKC
bit in the Wake Up Filter Control (WUFC) register. Instead, it is
determined by the APM settings in the WUC register (see
Section
This bit is loaded from NVM.
Flexible TCO Filter 1 Allocation
1b = Allocate flex TCO1 filter for wake.
0 b= Allocate flex TCO1 filter for manageability.
Flexible TCO Filter 1 Enable
When set, flex TCO1 filter is enabled for wake up. When cleared, flex
TCO1 filter is disabled. This bit takes affect only when the FTFA1 bit is
set (for example, flex TCO1 filter is allocated for APM wake).
Flexible TCO Filter 0 Allocation
1b = Allocate flex TCO0 filter for wake.
0b = Allocate flex TCO0 filter for manageability.
Flexible TCO Filter 0 Enable
When set, flex TCO0 filter is enabled for wake up. When cleared, flex
TCO0 filter is disabled. This bit takes affect only when the FTFA0 bit is
set (for example, flex TCO0 filter is allocated for wake).
Reserved.
10.2.7.36).
Description
Section
Section
5.5.1).
5.5.1).
Section 4.4.1
367