WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 297

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
10.2.2.3
Speed indicates the actual MAC speed configuration. These bits normally reflect the
speed of the actual link, negotiated by the PHY and link partner, and reflected internally
from the PHY to the MAC (SPD_IND). These bits might represent the speed
configuration of the MAC only, if the MAC speed setting has been forced via software
(CTRL.SPEED) or MAC auto-speed detection used. Speed indications are mapped as
follows:
00b = 10 Mb/s
01b = 100 Mb/s
10b = 1000 Mb/s
11b = 1000 Mb/s
If Auto-Speed Detection is enabled, the device's speed is configured only once after the
link signal is asserted by the PHY.
The ASDV bits are provided for diagnostics purposes only. Even if the MAC speed
configuration is not set using this function (ASDE=0b), the ASD calculation can be
initiated by software writing a logic one to the CTRL_EXT.ASDCHK bit. The resultant
speed detection is reflected in these bits.
EEPROM/FLASH Control Register - EEC (0x00010; RW/RO)
EE_SK
EE_CS
EE_DI
EE_DO
FWE
EE_REQ
EE_GNT
Field
0
1
2
3
5:4
6
7
Bit(s)
0b
0b
0b
X
01b
0b
0b
Initial
Value
Clock input to the NVM
When EE_GNT is 1b, the EE_SK output signal is mapped to this bit
and provides the serial clock input to the NVM. Software clocks the
NVM via toggling this bit with successive writes.
Chip select input to the NVM
When EE_GNT is 1b, the EE_CS output signal is mapped to the chip
select of the NVM device. Software enables the NVM by writing a 1b to
this bit.
Data input to the NVM
When EE_GNT is 1b, the EE_DI output signal is mapped directly to
this bit. Software provides data input to the NVM via writes to this bit.
Data output bit from the NVM
The EE_DO input signal is mapped directly to this bit in the register
and contains the NVM data output. This bit is read-only from the
software perspective – writes to this bit have no effect.
Flash Write Enable Control
These two bits control whether writes to the Flash are allowed.
00b = Enable Flash erase and block erase.
01b = Flash writes and Flash erase disabled.
10b = Flash writes enabled.
11b = Not allowed.
This field enables write and erase instructions from software to the
Flash via the Flash BAR and the software DMA registers (FLSW).
Request NVM Access
Software must write a 1b to this bit to get direct NVM access. It has
access when EE_GNT is 1b. When software completes the access it
must write a 0b.
Grant NVM Access
When this bit is set to 1b, software can access the NVM using the SK,
CS, DI, and DO bits.
Description
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