WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 352

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.7
Note:
Note:
Note:
10.2.7.1
10.2.7.2
352
The transmit interrupt delay timer (TIDV) can be used to coalesce transmit interrupts.
However, it might be necessary to ensure that no completed transmit remains
unnoticed for too long an interval in order to ensure timely release of transmit buffers.
This register can be used to ENSURE that a transmit interrupt occurs at some pre-
defined interval after a transmit completes. Like the delayed-transmit timer, the
absolute transmit timer ONLY applies to transmit descriptor operations where
This feature operates by initiating a count-down timer upon successfully transmitting
the buffer. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is
generated. The occurrence of either an immediate (non-scheduled) or delayed transmit
timer (TIDV) expiration interrupt halts the TADV timer and eliminates any spurious
second interrupts.
Setting the value to zero, disables the transmit absolute delay function. If an
immediate (non-scheduled) interrupt is desired for any transmit descriptor, the
descriptor IDE should be set to 0b.
Statistic Register Descriptions
All statistics registers reset when read. In addition, they stick at 0xFFFF_FFFF when the
maximum value is reached.
For the receive statistics it should be noted that a packet is indicated as received if it
passes the device’s filters and is placed into the packet buffer memory. A packet does
not have to be DMA’d to host memory in order to be counted as received.
Due to divergent paths between interrupt-generation and logging of relevant statistics
counts, it might be possible to generate an interrupt to the system for a noteworthy
event prior to the associated statistics count actually being incremented. This is
extremely unlikely due to expected delays associated with the system interrupt-
collection and ISR delay, but might be observed as an interrupt for which statistics
values do not quite make sense. Hardware guarantees that any event noteworthy of
inclusion in a statistics count is reflected in the appropriate count within 1 s; a small
time-delay prior to read of statistics might be necessary to avoid the potential for
receiving an interrupt and observing an inconsistent statistics count as part of the ISR.
CRC Error Count - CRCERRS (0x04000; R)
Counts the number of receive packets with CRC errors. In order for a packet to be
counted in this register, it must pass address filtering and must be 64 bytes or greater
(from <Destination Address> through <CRC>, inclusively) in length. If receives are not
enabled, then this register does not increment.
Alignment Error Count - ALGNERRC (0x04004; R)
CEC
AEC
1. Interrupt-based reporting is requested (RS set).
2. The use of the timer function is requested (IDE is set).
Field
Field
31:0
31:0
Bit(s)
Bit(s)
0x0
0x0
Initial
Initial
Value
Value
CRC Error Count
Alignment Error Count
82574 GbE Controller—Driver Programing Interface
Description
Description