ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 19

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
8.3 DMA mode
The ISP1362 also provides DMA mode for external microprocessors to access the
internal buffer memory of the ISP1362. The DMA operation enables data to be transferred
between the system memory of a microprocessor and the internal buffer memory of the
ISP1362.
Remark: The DMA operation must be controlled by the DMA controller of the external
microprocessor system (master).
microprocessor system and the ISP1362.
The ISP1362 provides two DMA channels. DMA channel 1 (controlled by the DREQ1 and
DACK1 signals) is for the DMA transfer between the system memory of a microprocessor
and the internal buffer memory of the ISP1362 host controller. DMA channel 2 (controlled
by the DREQ2 and DACK2 signals) is for the DMA transfer between the system memory
of a microprocessor and the internal buffer memory of the ISP1362 peripheral controller.
The ISP1362 provides an internal End-Of-Transfer (EOT) signal to terminate the DMA
transfer.
Fig 8.
Fig 9.
PIO interface between a microprocessor and the ISP1362
DMA interface between a microprocessor and the ISP1362
PROCESSOR
Rev. 07 — 29 September 2009
PROCESSOR
MICRO-
MICRO-
D [ 15:0 ]
DREQ1
DREQ2
DACK1
DACK2
D [ 15:0 ]
IRQ1
IRQ2
Figure 9
WR
RD
CS
WR
A2
A1
RD
microprocessor
microprocessor
bus interface
bus interface
shows the DMA interface between a
Single-chip USB OTG controller
D [ 15:0 ]
RD
WR
DACK1
DREQ1
DACK2
DREQ2
D [ 15:0 ]
RD
WR
CS
A1
A0
INT1
INT2
ISP1362
ISP1362
004aaa042
004aaa043
© ST-ERICSSON 2009. All rights reserved.
ISP1362
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