ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 67

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

14. Host controller registers
Table 35.
ISP1362_7
Product data sheet
Command (Hex)
Read
00
01
02
03
04
05
0D
0E
0F
11
Host controller registers overview
83
84
8F
Write
not applicable HcRevision
81
82
85
8D
8E
91
Table 34.
The host controller contains a set of on-chip control registers. These registers can be read
or written by the Host Controller Driver (HCD). The operational registers are made
compatible to Open Host Controller Interface (OHCI) operational registers. This enables
the OHCI HCD to be easily ported to the ISP1362.
Reserved bits may be defined in future releases of this specification. To ensure
interoperability, the HCD that does not use a reserved field must not assume that the
reserved field contains logic 0. Furthermore, the HCD must always preserve the values of
the reserved field. When a R/W register is modified, the HCD must first read the register,
modify the desired bits and then write the register with the reserved bits still containing the
read value. Alternatively, the HCD can maintain an in-memory copy of previously written
values that can be modified and then written to the host controller register. When there is
a write to set or clear the register, bits written to reserved fields must be logic 0.
As shown in
operational registers (32-bit registers) are similar to those defined in the OHCI
specification. The addresses, however, are equal to offset divided by 4.
Bit
31
30 to 24
23 to 0
Register
HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcFmInterval
HcFmRemaining
HcFmNumber
HcLSThreshold
OtgAltTimer register: bit description
Symbol
START_
TMR
-
CURRENT_
TIME
Table
35, the offset locations (commands to read registers) of these
Rev. 07 — 29 September 2009
Description
This is the start or stop bit of the OTG timer 2. Writing logic 1 will
cause OTG timer 2 to start counting from 0. When the counter reaches
FF FFFFh, this bit is auto-cleared (the counter is stopped). Writing
logic 0 will stop the counting.
If any bit of the OTGInterrupt register is set and the corresponding bit
of the OtgInterruptEnable register is also set, this bit will be
auto-cleared and the current value of the counter will be written to the
CURRENT_TIME field.
0 — stop the timer
1 — start the timer
reserved
When read, these bits give the current value of the timer. The actual
time is CURRENT_TIME × 0.01 ms.
Width Reference
32
32
32
32
32
32
32
32
32
32
Section 14.1.1 on page 69
Section 14.1.2 on page 69
Section 14.1.3 on page 71
Section 14.1.4 on page 72
Section 14.1.5 on page 73
Section 14.1.6 on page 74
Section 14.2.1 on page 75
Section 14.2.2 on page 76
Section 14.2.3 on page 77
Section 14.2.4 on page 78
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
ISP1362
Functionality
HC control and
status registers
HC frame
counter
registers
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