ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 48

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
11.8.4 Overcurrent detection circuit using external 5 V power source in OTG mode
11.9 ISP1362 host controller power management
In OTG mode using external 5 V power source for V
the same as that for non-OTG mode (see
In the ISP1362, the host controller and the peripheral controller are suspended and woken
up individually. The H_SUSPEND/H_WAKEUP and D_SUSPEND/D_WAKEUP pins must
be pulled-up by a large resistor (100 kΩ). In the suspend state, these pins are HIGH. To
wake up the host controller, these pins must be pulled LOW.
The ISP1362 can partially be suspended (only the host controller or only the peripheral
controller). In the partially suspended state, the clock circuit and PLL continue to work. To
save power, both the host controller and the peripheral controller must be set to suspend
mode.
The host controller can be suspended by writing 0680h (operational) and then 06C0h
(suspend) to the HcControl register.
The host controller can be set awake by one of the following ways:
On waking up from the suspend state, the clock to the host controller will sustain for 5 ms.
Within this 5 ms, the HCD must set the host controller to operational mode by writing
0680h to the HcControl register. If the HcControl register remains in the suspend state
(06C0h) after waking up the host controller, the host controller will return to the suspend
state after 5 ms.
Fig 25. Using internal charge pump
•
•
•
A LOW pulse on the H_SUSPEND/H_WAKEUP pin, minimum length of pulse is
25 ns.
A LOW pulse on the chip select (CS) pin, minimum length of pulse is 25 ns.
A ‘resume’ signal by USB devices connected to the downstream port.
(1) 100 μF for the host port, or 4.7 μF for the OTG port.
chassis
chassis
V
GND
BUS
DM
DP
1
2
3
4
5
6
Rev. 07 — 29 September 2009
DGND
DGND
C41 (1)
DGND
C17
0.1 μF
Section 11.8.1
FB2
BUS
Single-chip USB OTG controller
, the circuit and the operation are
and
Section
n.c.
© ST-ERICSSON 2009. All rights reserved.
11.8.2).
ISP1362
004aaa150
H_OCn
V
H_PSWn
BUS
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