ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 99

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

Table 91.
Table 92.
Table 93.
ISP1362_7
Product data sheet
Bit
31 to 0
Bit
31 to 0
Bit
31 to 0 LastPTDBits[31:0]
Symbol
Symbol
PTDDoneBits[31:0] R
HcINTLPTDDoneMap register: bit description
HcINTLPTDSkipMap register: bit description
HcINTLLastPTD register: bit description
Symbol
SkipBits[31:0] R/W
14.8.5 HcINTLPTDSkipMap register (R/W: 18h/98h)
14.8.6 HcINTLLastPTD register (R/W: 19h/99h)
on. The register is updated once every ms by the host controller and is cleared on read by
the HCD. Bits that are set represent its corresponding PTDs are processed by the host
controller and the ACK token is received from the device.
Code (Hex): 17 — read only
This is a 32-bit register, and the bit description is given in
represents the first PTD stored in the INTL buffer, bit 1 represents the second PTD stored
in the buffer, and so on. When a bit is set by the HCD, the corresponding PTD is skipped
and is not processed by the host controller. The host controller processes the skipped
PTD if the HCD has reset its corresponding skipped bit to logic 0. Clearing the
corresponding bit in the HcINTLPTDSkipMap register when there is no valid data in the
block will cause unpredictable behavior of the host controller.
Code (Hex): 18 — read
Code (Hex): 98 — write
This is a 32-bit register, and
represents the first PTD stored in the INTL buffer, bit 1 represents the second PTD stored
in the buffer, and so on. The bit that is set to logic 1 by the HCD is used as an indication to
the host controller that its corresponding PTD is the last PTD stored in the INTL buffer.
When the processing of the last PTD is complete, the host controller proceeds to process
ATL transactions.
Code (Hex): 19 — read
Code (Hex): 99 — write
Access
Access
R/W
Access
Value
0000h
Value
0000h
Value
0000h
Rev. 07 — 29 September 2009
Description
0 — The host controller processes the PTD.
1 — The host controller skips processing the PTD.
Description
0 — The PTD is not the last PTD stored in the buffer.
1 — The PTD is the last PTD stored in the buffer.
Description
0 — The PTD stored in the INTL buffer has not successfully been
processed by the host controller.
1 — The PTD stored in the INTL buffer has successfully been
processed by the host controller.
Table 93
shows its bit description. Bit 0 of the register
Single-chip USB OTG controller
Table
92. Bit 0 of the register
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