ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 36

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
10.4.3 HNP implementation and OTG state machine
The OTG state machine is the software behind all the OTG functionality. It is implemented
in the microprocessor system that is connected to the ISP1362. The ISP1362 provides all
input status, the output control and timers to fully support the state machine transitions in
Figure 18
These registers include:
The OTG interrupt is generated on the INT1 pin. It is shared with the host controller
interrupt. To enable the OTG interrupt, perform these steps:
Fig 19. Dual-role B-device state diagram
•
•
•
•
•
OtgControl register: provides control to V
line pull-up or pull-down, SRP detection, and so on.
OtgStatus register: provides status detection on V
V
OtgInterrupt register: provides interrupts for status change in OtgStatus register bits
and the OtgTimer time-out event.
OtgInterruptEnable register: provides interrupt mask for OtgInterrupt register bits.
OtgTimer register: provides 0.01 ms base programmable timer for use in the OTG
state machine.
BUS
chrg_vbus/
loc_conn/
session valid, session end, overcurrent, bus status.
START
loc_sof
b_host
and
a_conn
Figure
b_wait_acon
b_sess_vld/
chrg_vbus/
loc_conn/
loc_sof/
id/ |
Rev. 07 — 29 September 2009
19.
b_sess_vld/
id/ |
b_ase0_brst_tmout
a_bus_resume |
a_bus_suspend
b_bus_req/ |
chrg_vbus/
b_bus_req &
b_hnp_en &
drv_vbus/
loc_conn/
loc_sof/
a_conn/
b_sess_vld/
b_idle
BUS
id/ |
driving, charging or discharging, data
BUS
Single-chip USB OTG controller
and data lines including ID,
id/
b_srp_done
b_sess_end &
id/ |
b_bus_req &
b_se0_srp
b_peripheral
chrg_vbus/
b_sess_vld
© ST-ERICSSON 2009. All rights reserved.
loc_conn
loc_sof/
pulse chrg_vbus
ISP1362
pulse loc_conn
chrg_vbus/
drv_vbus/
loc_conn/
b_srp_init
loc_sof/
loc_sof/
a_idle
004aaa078
36 of 147