MC88LV926EGR2 IDT, Integrated Device Technology Inc, MC88LV926EGR2 Datasheet

MC88LV926EGR2

Manufacturer Part Number

MC88LV926EGR2

Description

IC PLL CLOCK DRIVER 20-SOIC

Manufacturer

IDT, Integrated Device Technology Inc

Type

PLL Clock Driverr

Datasheet

1.MC88LV926EGR2.pdf (11 pages)

Specifications of MC88LV926EGR2

Input

TTL

Output

CMOS, TTL

Frequency - Max

66MHz

Voltage - Supply

3 V ~ 3.6 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

20-SOIC

Frequency-max

66MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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IDT™ Low Skew CMOS PLL 68060 Clock Driver

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

Low Skew CMOS PLL 68060 Clock

Driver

Freescale Semiconductor

Technical Data

Low Skew CMOS PLL 68060

Clock Driver

low skew outputs' frequency and phase onto an input reference clock. It is

designed to provide clock distribution for CISC microprocessor or single

processor RISC systems. The RST_IN/RST_OUT(LOCK) pins provide a

processor reset function designed specifically for the MC68/EC/LC030/040/060

microprocessor family. To support the 68060 processor, the 88LV926 operates

from a 3.3 V supply.

input and distribute it to multiple locations on a board. The PLL also allows the

MC88LV926 to multiply a low frequency input clock and distribute it locally at a

higher (2X) system frequency.

Features

•

the ‘Q' output frequency. The 2X_Q output is ideal for 68060 systems which require a 2X processor clock input, and it meets the

tight duty cycle spec of the 50 and 66 MHz 68060. The QCLKEN output is designed to drive the CLKEN input of the 68060 when

the bus logic runs at half of the microprocessor clock rate. The QCLKEN output is skewed relative to the 2X_Q output to ensure

that CLKEN setup and hold times of the 68060 are satisfied. A Q/2 frequency is fed back internally, providing a fixed 2X

multiplication from the ‘Q' outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is provided)

the input/output frequency relationships are fixed. The Q3 output provides an inverted clock output to allow flexibility in the clock

tree design.

88LV926 in a static ‘test mode'. In this mode there is no frequency limitation on the input clock, which is necessary for a low

frequency board test environment.

pin will be pulled actively low until phase-lock is achieved. When phase-lock occurs, the RST_OUT(LOCK) is released and a pull-

up resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the RST_OUT(LOCK)

pin will stay low for 1024 cycles of the ‘Q' output frequency after the RST_IN pin is brought back high.

Description of the RST_IN/RST_OUT(LOCK) Functionality

as a lock indicator. If the RST_IN pin is held high during system power-up, the RST_OUT pin will be in the low state until steady

state phase/frequency lock to the input reference is achieved. 1024 ‘Q' output cycles after phase-lock is achieved the

RST_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull-up resistor (see the AC/

DC specs for the characteristics of the RST_OUT(LOCK) pin). If the RST_IN pin is held low during power-up, the

RST_OUT(LOCK) pin will remain low.

The MC88LV926 Clock Driver utilizes phase-locked loop technology to lock its

The PLL allows the high current, low skew outputs to lock onto a single clock

Three ‘Q' outputs (Q0-Q2) are provided with less than 500 ps skew between their rising edges. A 2X_Q output runs at twice

In normal phase-locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the

The RST_OUT(LOCK) pin doubles as a phase-lock indicator. When the RST_IN pin is held high, the open drain RST_OUT

The RST_IN and RST_OUT(LOCK) pins provide a 68030/040/060 processor reset function, with the RST_OUT pin also acting

Microprocessor PCLK Input Specifications

Less than 600 ps (Derived from the T

Part-to-Part Skew)

with V

20-Lead SOIC Pb-Free Package Available

2X_Q Output Meets All Requirements of the 50 and 66 MHz 68060

Low Voltage 3.3 V V

Three Outputs (Q0–Q2) with Output–Output Skew <500 ps

CLKEN Output for Half Speed Bus Applications

The Phase Variation from Part-to-Part Between SYNC and the ‘Q' Outputs Is

SYNC Input Frequency Range from 5.0 MHz to 2X_Q F

All Outputs Have ± 36 mA Drive (Equal High and Low) CMOS Levels

Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL-Level Compatible

Test Mode Pin (PLL_EN) Provided for Low Frequency Testing

= 3.3 V

Specification, Which Defines the

Max

20-LEAD PLASTIC SOIC PACKAGE

Document Number: MC88LV926

LOW SKEW CMOS PLL

68080 CLOCK DRIVER

MC88LV926

Pb-FREE PACKAGE

CASE 751D-06

DW SUFFIX

EG SUFFIX

DATA SHEET

Rev. 7, 4/2006

MC88LV926

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MC88LV926EGR2 Summary of contents

Page 1

Freescale Semiconductor Technical Data Low Skew CMOS PLL 68060 Clock Low Skew CMOS PLL 68060 Driver Clock Driver The MC88LV926 Clock Driver utilizes phase-locked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock. ...

Page 2

MC88LV926 Low Skew CMOS PLL 68060 Clock Driver Description of the RST_IN/RST_OUT(LOCK) Functionality (continued) After the system start-up is complete and the 88LV926 is phase-locked to the SYNC input signal (RST_OUT high), the processor reset functionality can be utilized. When ...

Page 3

MC88LV926 Low Skew CMOS PLL 68060 Clock Driver (1) Table 2. Maximum Ratings Symbol DC Supply Voltage Referenced to GND Input Voltage (Referenced to GND Output Voltage (Referenced to GND) V ...

Page 4

MC88LV926 Low Skew CMOS PLL 68060 Clock Driver Lock Indicator RST_IN RESET_OUT SYNC1 PFD PLL_EN ÷8 Power–On Reset MR Table 5. Sync Input Timing Requirements Symbol t Rise/Fall Time, SYNC Input RISE/FALL From 0.8V to 2.0V SYNC Input t , ...

Page 5

MC88LV926 Low Skew CMOS PLL 68060 Clock Driver Table 6. Frequency Specifications (T Symbol Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output Fmax (‘Q') Maximum Operating Frequency, Q0–Q3 Outputs NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase-locked ...

Page 6

MC88LV926 Low Skew CMOS PLL 68060 Clock Driver 1. Statistical characterization techniques were used to guarantee those specifications which cannot be measured on the ATE. MC88LV926 units were fabricated with key transistor properties intentionally varied to create a 14 cell ...

Page 7

MC88LV926 Low Skew CMOS PLL 68060 Clock Driver 12.5 MHz Crystal Oscillator Figure 5. Logical Representation of the MC88LV926 With Input/Output Frequency Relationships SYNC Input t SKEWall Q0–Q3 Outputs 2X_Q Output QCLKEN t SKEWQCLKEN NOTES: 1. The MC88LV926 aligns rising ...

Page 8

MC88LV926 Low Skew CMOS PLL 68060 Clock Driver 1. Figure 7 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free operation: 1a. All ...

Page 9

MC88LV926 Low Skew CMOS PLL 68060 Clock Driver 16.67 MHz X–TAL Oscillator System Reset Figure 8. Typical MC88LV926/MC68060 System Configuration IDT™ Low Skew CMOS PLL 68060 Clock Driver Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired ...

Page 10

MC88LV926 Low Skew CMOS PLL 68060 Clock Driver 10.55 10X 10.05 PIN 0.25 M NUMBER 1 PIN 1 INDEX 10 7.6 7.4 5 0.75 X45˚ 0.25 MC88LV926 IDT™ Low Skew CMOS PLL 68060 Clock Driver Freescale Timing Solutions Organization has ...

Page 11

MPC92459 MC88LV926 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer Low Skew CMOS PLL 68060 Clock Driver INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 ...

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