MC88LV926EGR2 IDT, Integrated Device Technology Inc, MC88LV926EGR2 Datasheet - Page 2

• Manufacturer Part Number: MC88LV926EGR2
• Description: IC PLL CLOCK DRIVER 20-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88LV926EGR2

• Input: TTL
• Output: CMOS, TTL
• Frequency - Max: 66MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC
• Frequency-max: 66MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Low Skew CMOS PLL 68060 Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
Description of the RST_IN/RST_OUT(LOCK)
Functionality (continued)
phase-locked to the SYNC input signal (RST_OUT high), the
processor reset functionality can be utilized. When the
RST_IN pin is toggled low (min. pulse width=10 nS),
RST_OUT(LOCK) will go to the low state and remain there
for 1024 cycles of the ‘Q' output frequency (512 SYNC
cycles). During the time in which the RST_OUT(LOCK) is
actively pulled low, all the 88LV926 clock outputs will continue
operating correctly and in a locked condition to the SYNC
input (clock signals to the 68030/040/060 family of
processors must continue while the processor is in reset). A
propagation delay after the 1024th cycle RST_OUT(LOCK)
goes back to the high impedance state to be pulled high by
the resistor.
Processor Reset Operation During System Start-up
Table 1. Capacitance and Power Specifications
MC88LV926
2
C
C
PD
PD
1. Value at V
IN
PD
After the system start-up is complete and the 88LV926 is
Power Supply Ramp Rate Restriction for Correct 030/040
1
2
Symbol
CC
= 3.3 V TBD
Input Capacitance
Power Dissipation Capacitance
Power Dissipation at 33MHz With 50Ω
Thevenin Termination
Power Dissipation at 33MHz With 50Ω
Parallel Termination to GND
Figure 1. Pinout: 20-Lead Wide SOIC Package (Top View)
Parameter
GND(AN)
V
RST_IN
CC
SYNC
GND
(AN)
RC1
V
MR
Q3
Q0
CC
10
1
2
3
4
5
6
7
8
9
2
37.5mW/Output
15mW/Output
Value Type
225mW/Device
90mW/Device
phase-lock to the reference source, some constraints must
be placed on the power supply ramp rate to make sure the
RST_OUT(LOCK) signal holds the processor in reset during
system start-up (power-up). With the recommended loop filter
values (see
The phase-lock loop will begin attempting to lock to a
reference source (if it is present) when V
V
PLL could lock to the reference source, causing
RST_OUT(LOCK) to go high before the 88LV926 and 030/
040 processor is fully powered up, violating the processor
reset specification. Therefore, if it is necessary for the
RST_IN pin to be held high during power-up, the V
rate must be less than 10 mS for proper 68030/040/060 reset
operation.
can be held low during system start-up (which holds
RST_OUT low). The RST_OUT(LOCK) pin will then be pulled
back high 1024 cycles after the RST_IN pin goes high.
CC
4.5
40
This ramp rate restriction can be ignored if the RST_IN pin
Because the RST_OUT(LOCK) pin is an indicator of
(1)
(1)
ramp rate is significantly slower than 10 ms, then the
20
19
18
17
16
15
14
13
12
11
(1)
(1)
GND
2X_Q
QCLKEN
V
Q2
GND
RST_OUT(LOCK)
PLL_EN
Q1
V
CC
CC
Figure
7) the lock time is approximately 10ms.
Unit
mW
mW
pF
pF
Advanced Clock Drivers Device Data
V
V
V
T = 25°C
V
T = 25°C
CC
CC
CC
CC
Freescale Semiconductor
= 3.3 V
= 3.3 V
= 3.3 V
= 3.3 V
Test Conditions
CC
reaches 2 V. If the
CC
ramp
NETCOM
MC88LV926