MC88LV926EGR2 IDT, Integrated Device Technology Inc, MC88LV926EGR2 Datasheet - Page 8

• Manufacturer Part Number: MC88LV926EGR2
• Description: IC PLL CLOCK DRIVER 20-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88LV926EGR2

• Input: TTL
• Output: CMOS, TTL
• Frequency - Max: 66MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC
• Frequency-max: 66MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Low Skew CMOS PLL 68060 Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
8
1.
1a. All loop filter and analog isolation components should
1b. The 47 Ω resistors, the 10 μF low frequency bypass
MC88LV926
NOTE: Further loop optimization may occur.
Figure 7
scheme which will be effective in most applications. The
following guidelines should be followed to ensure stable
and jitter-free operation:
be tied as close to the package as possible. Stray
current passing through the parasitics of long traces can
cause undesirable voltage transients at the RC1 pin.
capacitor, and the 0.1 μF high frequency bypass
capacitor form a wide bandwidth filter that will make the
88LV926 PLL insensitive to voltage transients from the
system digital V
will typically ensure that a 100mV step deviation on the
digital V
phase deviation on the 88LV926 outputs. A 250 mV
step deviation on V
values will cause no more than a 250 ps phase
deviation; if a 25 μF bypass capacitor is used (instead of
10 μF) a 250 mV V
100 ps phase deviation.
If good bypass techniques are used on a board design
near components which may cause digital V
ground noise, the above described V
should not occur at the 88LV926's digital V
The purpose of the bypass filtering scheme shown in
CC
shows a loop filter and analog isolation
supply will cause no more than a 100 ps
Figure 7. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV926
10 μF Low
CC
Freq Bias
supply and ground planes. This filter
CC
CC
step will cause no more than a
using the recommended filter
0.1 μF High
Freq Bias
NOTES CONCERNING LOOP FILTER AND
CC
step deviations
CC
470 KΩ or
BOARD LAYOUT ISSUES
47 Ω
CC
1 MΩ
supply.
and
47 Ω
Board GND
Board V
0.1 μF (Loop Filter
CC
8
330 Ω
Cap)
1c. There are no special requirements set forth for the loop
1d. The 470 K reference resistor injects current into the
2.
A separate Analog power suppy is not necessary and should not be used.
Following these prescribed guidelines is all that is necessary to use the
MC88LV926 in a normal digital environment.
Figure 6
from the power supply and ground plane transients that
can occur in a high frequency, high speed digital system.
filter resistors (470 K and 33 0Ω). The loop filter
capacitor (0.1uF) can be a ceramic chip capacitor, the
same as a standard bypass capacitor.
internal charge pump of the PLL, causing a fixed offset
between the outputs and the SYNC input. This also
prevents excessive jitter caused by inherent PLL dead–
band. If the VCO (2X_Q output) is running above
40 MHz, the 470 K resistor provides the correct amount
of current injection into the charge pump (2–3 μA). If the
VCO is running below 40 MHz, a 1 MΩ reference
resistor should be used (instead of 470 K).
In addition to the bypass capacitors used in the analog
filter of
capacitor between each of the other (digital) four V
pins and the board ground plane. This will reduce output
switching noise caused by the 88LV926 outputs, in
addition to reducing potential for noise in the ‘analog'
section of the chip. These bypass capacitors should
also be tied as close to the 88LV926 package as
possible.
5
6
7
Figure
RC1
Analog GND
is to give the 88LV926 additional protection
Analog V
7, there should be a 0.1 μF bypass
CC
Advanced Clock Drivers Device Data
Analog Loop Filter/VCO Section
of the MC88LV926 20-Pin SOIC
Package (not drawn to scale)
Freescale Semiconductor
NETCOM
CC
MC88LV926