MC88LV926EGR2 IDT, Integrated Device Technology Inc, MC88LV926EGR2 Datasheet - Page 5

• Manufacturer Part Number: MC88LV926EGR2
• Description: IC PLL CLOCK DRIVER 20-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88LV926EGR2

• Input: TTL
• Output: CMOS, TTL
• Frequency - Max: 66MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC
• Frequency-max: 66MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Low Skew CMOS PLL 68060 Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
Advanced Clock Drivers Device Data
Freescale Semiconductor
Table 6. Frequency Specifications (T
NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase-locked condition.
Table 7. AC Characteristics (T
Fmax (2X_Q)
Fmax (‘Q')
t
All Outputs
t
2X_Q Output
t
(Q0, Q1, Q2, Q3)
t
(2X_Q Output)
t
(Rising)
t
(Falling)
t
t
(2)
t
t
t
SYNC
t
t
LOW
t
t
1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this
2. Under equally loaded conditions and at a fixed temperature and voltage.
3. Guaranteed that QCLKEN will meet the setup and hold time requirement of the 68060.
4. With V
5. Specification is valid only when the PLL_EN pin is low.
6. See
RISE/FALL
RISE/FALL
pulse width(a)
pulse width(b)
SKEWr
SKEWf
SKEWall
SKEW
LOCK
PHL
REC
W
W
PZL
PLZ
, MR LOW
, RST_IN
methodology.
(1)
(1)
Symbol
, MR to
MR – Q
Symbol
(1)
(4)
QCLKEN
(1)(5)
(2)
(2)
(2)
Application
CC
(1)
(1)
(1)
(1) (5)
fully powered–on: t
(1)
Maximum Operating Frequency, 2X_Q Output
Maximum Operating Frequency,
Q0–Q3 Outputs
Notes, Note 4 for the distribution in time of each output referenced to SYNC.
Rise/Fall Time, into 50Ω Load
Rise/Fall Time into a 50Ω Load
Output Pulse Width
Q0, Q1, Q2, Q3 at 1.65V
Output Pulse Width
2X_Q at 1.65V
Output–to–Output Skew
Between Outputs Q0–Q2
(Rising Edge Only)
Output–to–Output Skew
Between Outputs Q0–Q2
(Falling Edge Only)
Output–to–Output Skew
2X_Q, Q0–Q2, Q3
Output–to–Output Skew
QCLKEN to 2X_Q
Phase–Lock Acquisition Time,
All Outputs to SYNC Input
Propagation Delay,
MR to Any Output (High–Low)
Reset Recovery Time rising MR edge to
falling SYNC edge
Minimum Pulse Width, MR input Low
Minimum Pulse Width, RST_IN Low
Output Enable Time
RST_IN Low to RST_OUT Low
Output Enable Time
RST_IN High to RST_OUT High Z
CLOCK
Parameter
A
= 0°C to 70°C; V
(6)
Max is with C1 = 0.1 μF; t
A
2X_Q = 66 MHz
2X_Q = 50 MHz
= 0°C to 70°C; V
Parameter
CC
= 3.3V ± 0.3V
CC
LOCK
(508 Q/2 Cycles)
1016 ‘Q' Cycles
0.5t
0.5t
Minimum
= 3.3 V ± 0.3 V
cycle
cycle
5
9.7
7.0
Min is with C1 = 0.01 μF.
0.3
0.5
1.5
1.5
10
–
–
–
1
9
5
(3)
(3)
– 0.5
– 0.5
(512 Q/2 Cycles)
1024 ‘Q' Cycles
Maximum
0.5t
0.5t
cycle
cycle
13.5
16.5
500
750
1.6
1.6
1.0
10
–
–
–
–
+ 0.5
+ 0.5
Guaranteed Minimum
Unit
ms
ns
ns
ns
ns
ps
ns
ps
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
50 Ω Load Terminated to V
2 (See Application Note 3)
50 Ω Load Terminated to V
2 (See Application Note 3)
Into a 50Ω Load Terminated to
V
Figure
Into a 50 Ω Load Terminated to
V
Figure
Into a 50 Ω Load Terminated to
V
Figure
Into a 50 Ω Load Terminated to
V
Figure
Into a 50 Ω Load
Terminated to V
When in Phase–Lock
See
See
RISE
FALL
RISE
FALL
CC
CC
CC
CC
66
33
/2 (See Timing Diagram in
/2 (See Timing Diagram in
/2 (See Timing Diagram in
/2 (See Timing Diagram in
Application
Application
– 0.8 V to 2.0 V
– 0.8 V to 2.0 V
– 2.0 V to 0.8 V
– 2.0 V to 0.8 V
6)
6)
6)
6)
Condition
CC
Notes,
Notes,
MC88LV926
/2
Note 5
Note 5
Unit
MHz
MHz
NETCOM
CC
CC
MC88LV926
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