MC88LV926EGR2 IDT, Integrated Device Technology Inc, MC88LV926EGR2 Datasheet - Page 6

• Manufacturer Part Number: MC88LV926EGR2
• Description: IC PLL CLOCK DRIVER 20-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88LV926EGR2

• Input: TTL
• Output: CMOS, TTL
• Frequency - Max: 66MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC
• Frequency-max: 66MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Low Skew CMOS PLL 68060 Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
6
1.
2.
MC88LV926
Statistical characterization techniques were used to
guarantee those specifications which cannot be
measured on the ATE. MC88LV926 units were
fabricated with key transistor properties intentionally
varied to create a 14 cell designed experimental matrix.
IC performance was characterized over a range of
transistor properties (represented by the 14 cells) in
excess of the expected process variation of the wafer
fabrication area. IC performance to each specification
and fab variation were used to set performance limits of
ATE testable specifications within those which are to be
guaranteed by statistical characterization. In this way, all
units passing the ATE test will meet or exceed the non-
tested specifications limits.
A 470 KΩ or 1 MΩ resistor tied to either Analog V
Analog GND, as shown in
With the 470 KΩ resistor tied in this fashion, the T
measured at the input pins is:
Loop Filter
External
SYNC InputT
Q0 OutputT
t
PD
= 2.25 ns ± 1.0 ns (Typical Values)
Figure 3. Depiction of the Fixed SYNC to Q0 Offset (t
0.1 μF
2.25 ns
330 Ω
Offset
Figure
When a 470 KΩ Resistor Is Tied to V
RC1
3, is required to
Analog GND
R2
C1
PD
Internal
Logic
Figure 4. RST_OUT Test Circuit
specification
1 MΩ or 470 K Ω
Reference
Resistor
3 V
APPLICATION NOTES
CC
5 V
or
RST_OUT Pin
6
3.
Analog GND
With the 470 KΩ resistor tied in this fashion, the T
measured at the input pin is:
ensure no jitter is present on the MC88LV926 outputs.
This technique causes a phase offset between the
SYNC input and the Q0 output, measured at the pins.
The t
process, temperature, and voltage. The specs were
arrived at by measuring the phase relationship for the
14 lots described in note 1 while the part was in phase-
locked operation. The actual measurements were made
with a 10 MHz SYNC input (1.0 ns edge rate from 0.8 V
to 2.0 V). The phase measurements were made at
1.5 V. See
Two specs (t
see AC Specifications) guarantee that the MC88LV926
meets the 33 MHz and 66 MHz 68060 P-Clock input
specification.
C
1 K
CC
PD
L
1 MΩ or 470 KΩ
SYNC Input
Q0 Output
or Ground
spec describes how this offset varies with
Reference
Resistor
PD
V
Figure 3
CC
) Which Is Present
RISE/FALL
t
PD
Advanced Clock Drivers Device Data
= –0.80 ns ± 0.30 ns
for a graphical description.
Analog V
and t
0.1 μF
330 Ω
PULSE
CC
–0.8 ns
Analog GND
Offset
Freescale Semiconductor
RC1
Width 2X_Q output,
PD
R2
C1
specification
5 V
3 V
NETCOM
MC88LV926