MC88LV926EGR2 IDT, Integrated Device Technology Inc, MC88LV926EGR2 Datasheet - Page 7

• Manufacturer Part Number: MC88LV926EGR2
• Description: IC PLL CLOCK DRIVER 20-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88LV926EGR2

• Input: TTL
• Output: CMOS, TTL
• Frequency - Max: 66MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC
• Frequency-max: 66MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Low Skew CMOS PLL 68060 Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
Advanced Clock Drivers Device Data
Freescale Semiconductor
4.
5.
NOTES:
1.
2.
Q0–Q3 Outputs
The t
0°C to 70°C and the full V
the ΔT and ΔV
specification limits, the t
The RST
Therefore an external pull–up resistor must be provide
2X_Q Output
The MC88LV926 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a
50% duty cycle.
All skew specs are measured between the V
as “windows”, not as a ± deviation around a center point.
SYNC Input
QCLKEN
PD
Figure 5. Logical Representation of the MC88LV926 With Input/Output Frequency Relationships
spec includes the full temperature range from
_
OUT pin is an open drain N–Channel output.
CC
12.5 MHz
Oscillator
t
Crystal
SKEWQCLKEN
is a given system are less than the
Figure 6. Output/Input Switching Waveforms and Timing Relationships
t
PD
SKEWall
CC
spec window will be reduced.
range from 3.0 V to 3.3 V. If
SYNC
MR
PLL_EN
RST_IN
t
SKEWf
CC
/2 crossing point of the appropriate output edges. All skews are specified
RST_OUT
QCLKEN
t
CYCLE
2X_Q
7
Q0
Q1
Q2
Q3
SYNC Input
t
SKEWr
to pull up the RST
impedance state (after the MC88LV926 is phase-locked
to the reference input with RST
cycles after the RST
locked). In the t
resistor is used as a pull-up as shown in
Delay 33 MHz CLKEN Output
t
SKEWQCLKEN
66 MHz P–Clock
t
CYCLE
and System
Output
PLZ
B–Clock
33 MHz
Outputs
_
‘Q' Outputs
OUT pin when it goes into the high
t
and t
SKEWf
_
IN pin goes high when the part is
PZL
specifications, a 1 KΩ
_
IN held high or 1024 ‘Q'
t
Figure
SKEWr
MC88LV926
3.
NETCOM
MC88LV926
7