AD9511BCPZ Analog Devices Inc, AD9511BCPZ Datasheet - Page 15

• Manufacturer Part Number: AD9511BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9511BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9511/PCB - BOARD EVAL CLOCK DISTR 48LFCSPAD9511-VCO/PCB - BOARD EVAL CLOCK DISTR 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SERIAL CONTROL PORT
Table 8.
Parameter
CSB, SCLK (INPUTS)
SDIO (WHEN INPUT)
SDIO, SDO (OUTPUTS)
TIMING
FUNCTION PIN
Table 9.
Parameter
INPUT CHARACTERISTICS
RESET TIMING
SYNC TIMING
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Output Logic 1 Voltage
Output Logic 0 Voltage
Clock Rate (SCLK, 1/t
Pulse Width High, t
Pulse Width Low, t
SDIO to SCLK Setup, t
SCLK to SDIO Hold, t
SCLK to Valid SDIO and SDO, t
CSB to SCLK Setup and Hold, t
CSB Minimum Pulse Width High, t
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
Pulse Width Low
Pulse Width Low
PWL
PWH
DH
SCLK
DS
)
Min
2.0
50
1.5
DV
S
, t
H
PWH
Typ
110
2
Max
0.8
1
Unit
V
V
μA
μA
pF
ns
High speed clock cycles
Min
2.0
2.0
2.7
16
16
2
1
6
2
3
Rev. A | Page 15 of 60
Typ
110
2
10
10
2
Max
0.8
1
0.8
0.4
25
Test Conditions/Comments
The FUNCTION pin has a 30 kΩ internal pull-down resistor.
This pin should normally be held high. Do not leave NC.
High speed clock is CLK1 or CLK2, whichever is
used for distribution.
Unit
V
V
μA
μA
pF
V
V
nA
nA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
CSB and SCLK have 30 kΩ
internal pull-down resistors
AD9511