AD9511BCPZ Analog Devices Inc, AD9511BCPZ Datasheet - Page 5

• Manufacturer Part Number: AD9511BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9511BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9511/PCB - BOARD EVAL CLOCK DISTR 48LFCSPAD9511-VCO/PCB - BOARD EVAL CLOCK DISTR 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Parameter
NOISE CHARACTERISTICS
PLL DIGITAL LOCK DETECT WINDOW
1
2
3
4
CLOCK INPUTS
Table 2.
Parameter
CLOCK INPUTS (CLK1, CLK2)
1
2
3
REFIN and REFINB self-bias points are offset slightly to avoid chatter on an open input condition.
CLK2 is electrically identical to CLK1; the distribution only input can be used as differential or single-ended input (see the Clock Inputs section).
Example: −218 + 10 × log(f
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input.
With a 50 Ω termination, this is −12.5 dBm.
With a 50 Ω termination, this is +10 dBm.
In-Band Noise of the Charge Pump/
Phase Frequency Detector (In-Band
Means Within the LBW of the PLL)
PLL Figure of Merit
Required to Lock
To Unlock After Lock (Hysteresis)
Input Frequency
Input Sensitivity
Input Level
Input Common-Mode Voltage, V
Input Common-Mode Range, V
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
@ 50 kHz PFD Frequency
@ 2 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
(Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns Only)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
Low Range (ABP 1.3 ns, 2.9 ns Only)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
PFD
) + 20 × log(N) should give the values for the in-band noise at the VCO output.
1
CMR
CM
4
4
Min
Min
0
1.5
1.3
4.0
Typ
−172
−156
−149
−142
−218 +
10 × log (f
3.5
7.5
3.5
7
15
11
Typ
150
1.6
150
4.8
2
2
PFD
Max
1.6
2
1.7
1.8
5.6
Rev. A | Page 5 of 60
3
)
Max
Unit
GHz
mV p-p
V p-p
V
V
mV p-p
kΩ
pF
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
Jitter performance can be improved with higher slew
rates (greater swing).
Larger swings turn on the protection diodes and can
degrade jitter performance.
Self-biased; enables ac coupling.
With 200 mV p-p signal applied; dc-coupled.
CLK2 ac-coupled; CLK2B ac bypassed to RF ground.
Self-biased.
Test Conditions/Comments
The synthesizer phase noise floor is
estimated by measuring the in-band
phase noise at the output of the VCO and
subtracting 20logN (where N is the
N divider value).
Approximation of the PFD/CP phase noise
floor (in the flat region) inside the PLL loop
bandwidth. When running closed loop this
phase noise is gained up by 20 × log(N)
Signal available at STATUS pin
when selected by 08h<5:2>.
Selected by Register ODh.
<5> = 1b.
<5> = 0b.
<5> = 0b.
Selected by Register 0Dh.
<5> = 1b.
<5> = 0b.
<5> = 0b.
3
AD9511
.