AD9511BCPZ Analog Devices Inc, AD9511BCPZ Datasheet - Page 31

• Manufacturer Part Number: AD9511BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9511BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9511/PCB - BOARD EVAL CLOCK DISTR 48LFCSPAD9511-VCO/PCB - BOARD EVAL CLOCK DISTR 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Phase Frequency Detector (PFD) and Charge Pump
The PFD takes inputs from the R counter and the N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 36 is a
simplified schematic. The PFD includes a programmable delay
element that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. Two
bits in Register 0Dh <1:0> control the width of the pulse.
R DIVIDER
N DIVIDER
HI
HI
Figure 36. PFD Simplified Schematic and Timing (In Lock)
D1 Q1
D2 Q2
CLR1
CLR2
U1
U2
LOSS OF REFERENCE OR LOCK DETECT (ACTIVE HIGH)
LOSS OF REFERENCE OR LOCK DETECT (ACTIVE LOW)
PROGRAMMABLE
ANTIBACKLASH
UP
PULSE WIDTH
DOWN
ANALOG LOCK DETECT (N-CHANNEL OPEN DRAIN)
ANALOG LOCK DETECT (P-CHANNEL OPEN DRAIN)
DELAY
DIGITAL LOCK DETECT (ACTIVE HIGH)
DIGITAL LOCK DETECT (ACTIVE LOW)
LOSS OF REFERENCE (ACTIVE HIGH)
LOSS OF REFERENCE (ACTIVE LOW)
U3
PRESCALER OUTPUT (NCLK)
Figure 37. STATUS Pin Circuit CLK1 Clock Input
OFF (LOW) (DEFAULT)
A COUNTER OUTPUT
GND
V
N DIVIDER OUTPUT
R DIVIDER OUTPUT
P
PFD DOWN PULSE
CHARGE
PUMP
PFD UP PULSE
Rev. A | Page 31 of 60
TRI-STATE
CP
PLL MUX CONTROL
08h <5:2>
Antibacklash Pulse
The PLL features a programmable antibacklash pulse width that
is set by the value in Register 0Dh<1:0>. The default
antibacklash pulse width is 1.3 ns (0Dh<1:0> = 00b) and
normally should not need to be changed. The antibacklash
pulse eliminates the dead zone around the phase-locked
condition and thereby reduces the potential for certain spurs
that could be impressed on the VCO signal.
STATUS Pin
The output multiplexer on the AD9511 allows access to various
signals and internal points on the chip at the STATUS pin.
Figure 37 shows a block diagram of the STATUS pin section.
The function of the STATUS pin is controlled by Register
08h<5:2>.
PLL Digital Lock Detect
The STATUS pin can display two types of PLL lock detect:
digital (DLD) and analog (ALD). Whenever digital lock detect
is desired, the STATUS pin provides a CMOS level signal, which
can be active high or active low.
The digital lock detect has one of two time windows, as selected
by Register 0Dh<5>. The default (ODh<5> = 0b) requires the
signal edges on the inputs to the PFD to be coincident within
9.5 ns to set the DLD true, which then must separate by at least
15 ns to give DLD = false.
The other setting (ODh<5> = 1b) makes these coincidence
times 3.5 ns for DLD = true and 7 ns for DLD = false.
The DLD may be disabled by writing 1 to Register 0Dh<6>.
If the signal at REFIN goes away while DLD is true, the DLD
will not necessarily indicate loss-of-lock. See the Loss of
Reference section for more information.
SYNC DETECT ENABLE
DETECT
SYNC
58h <0>
GND
V
S
STATUS
PIN
AD9511