AD9511BCPZ Analog Devices Inc, AD9511BCPZ Datasheet - Page 56

• Manufacturer Part Number: AD9511BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9511BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9511/PCB - BOARD EVAL CLOCK DISTR 48LFCSPAD9511-VCO/PCB - BOARD EVAL CLOCK DISTR 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9511
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9511 offers both LVPECL and
LVDS outputs, which are better suited for driving long traces
where the inherent noise immunity of differential signaling
provides superior performance for clocking converters.
LVPECL CLOCK DISTRIBUTION
The low voltage, positive emitter-coupled, logic (LVPECL)
outputs of the AD9511 provide the lowest jitter clock signals
available from the AD9511. The LVPECL outputs (because they
are open emitter) require a dc termination to bias the output
transistors. A simplified equivalent circuit in
the LVPECL output stage.
In most applications, a standard LVPECL far-end termination is
recommended, as shown in Figure 56. The resistor network is
designed to match the transmission line impedance (50 Ω) and
the desired switching threshold (1.3 V).
3.3V
LVPECL
3.3V
LVPECL
200Ω
Figure 57. LVPECL with Parallel Transmission Line
Figure 56. LVPECL Far-End Termination
V
T
(NOT COUPLED)
SINGLE-ENDED
= V
0.1nF
0.1nF
200Ω
CC
50Ω
50Ω
– 1.3V
DIFFERENTIAL
(COUPLED)
127Ω
83Ω
3.3V
100Ω
Figure 41 shows
127Ω
83Ω
3.3V
LVPECL
3.3V
LVPECL
Rev. A | Page 56 of 60
LVDS CLOCK DISTRIBUTION
Low voltage differential signaling (LVDS) is a second
differential output option for the AD9511. LVDS uses a current
mode output stage with several user-selectable current levels.
The normal value (default) for this current is 3.5 mA, which
yields 350 mV output swing across a 100 Ω resistor. The LVDS
outputs meet or exceed all ANSI/TIA/EIA—644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 58.
See Application Note AN-586 on the ADI website at
www.analog.com
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
Many applications seek high speed and performance under less
than ideal operating conditions. In these application circuits,
the implementation and construction of the PCB is as
important as the circuit design. Proper RF techniques must be
used for device selection, placement, and routing, as well as for
power supply bypassing and grounding to ensure optimum
performance.
3.3V
LVDS
DIFFERENTIAL (COUPLED)
Figure 58. LVDS Output Termination
for more information on LVDS.
100Ω
100Ω
3.3V
LVDS