AD9511BCPZ Analog Devices Inc, AD9511BCPZ Datasheet - Page 26

• Manufacturer Part Number: AD9511BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9511BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9511/PCB - BOARD EVAL CLOCK DISTR 48LFCSPAD9511-VCO/PCB - BOARD EVAL CLOCK DISTR 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9511
TYPICAL MODES OF OPERATION
PLL WITH EXTERNAL VCXO/VCO FOLLOWED BY
CLOCK DISTRIBUTION
This is the most common operational mode for the AD9511.
An external oscillator (shown as VCO/VCXO) is phase locked
to a reference input frequency applied to REFIN. The loop filter
is usually a passive design. A VCO or a VCXO can be used. The
CLK2 input is connected internally to the feedback divider, N.
The CLK2 input provides the feedback path for the PLL. If the
VCO/VCXO frequency exceeds maximum frequency of the
output(s) being used, an appropriate divide ratio must be set in
the corresponding divider(s) in the Distribution Section. Some
power can be saved by shutting off unused functions, as well as
by powering down any unused clock channels (see the Register
Map and Description section).
REFERENCE
INPUT
Figure 30. PLL and Clock Distribution Mode
FUNCTION
SERIAL
PORT
CLK1
REFIN
V
REF
DIVIDE
DIVIDE
DIVIDE
DIVIDE
DIVIDE
R
N
AD9511
STATUS
Δ
T
PFD
LVDS/CMOS
LVDS/CMOS
LVPECL
LVPECL
LVPECL
REF
PLL
CLK2
CHARGE
PUMP
FILTER
CLOCK
OUTPUTS
VCXO,
LOOP
VCO
Rev. A | Page 26 of 60
CLOCK DISTRIBUTION ONLY
It is possible to use only the distribution section whenever the
PLL section is not needed. Some power can be saved by
shutting the PLL block off, as well as by powering down any
unused clock channels (see the Register Map Description
section).
In distribution mode, both the CLK1 and CLK2 inputs are
available for distribution to outputs via a low jitter multiplexer
(mux).
INPUT 1
CLOCK
FUNCTION
SERIAL
PORT
CLK1
REFIN
Figure 31. Clock Distribution Mode
V
REF
DIVIDE
DIVIDE
DIVIDE
DIVIDE
DIVIDE
R
N
AD9511
Δ
STATUS
T
PFD
LVDS/CMOS
LVDS/CMOS
LVPECL
LVPECL
LVPECL
REF
PLL
CLK2
CHARGE
PUMP
CLOCK
INPUT 2
CLOCK
OUTPUTS