AD9511BCPZ Analog Devices Inc, AD9511BCPZ Datasheet - Page 20

• Manufacturer Part Number: AD9511BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9511BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9511/PCB - BOARD EVAL CLOCK DISTR 48LFCSPAD9511-VCO/PCB - BOARD EVAL CLOCK DISTR 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9511
Table 13. Pin Function Descriptions
Pin No.
1
2
3, 6, 9, 18, 22,
23, 25, 28, 29,
32, 33, 36, 39,
40, 44, 48
4
5
7
8
10
11
12
13
14
15
16
17
19, 24, 37,
38, 43, 46
20
21
26
27
30
31
34
35
41
42
45
47
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be attached to ground, GND.
Mnemonic
REFIN
REFINB
VS
VCP
CP
CLK2
CLK2B
CLK1
CLK1B
FUNCTION
STATUS
SCLK
SDIO
SDO
CSB
GND
OUT2B
OUT2
OUT1B
OUT1
OUT4B
OUT4
OUT3B
OUT3
OUT0B
OUT0
RSET
CPRSET
Description
PLL Reference Input.
Complementary PLL Reference Input.
Power Supply (3.3 V).
Charge Pump Power Supply. It should be greater than or equal to VS.
VCP can be set as high as 5.5 V for VCOs, requiring extended tuning range.
Charge Pump Output.
Clock Input. Used to connect external VCO/VCXO to feedback divider, N. CLK2 also drives the
distribution section of the chip and may be used as a generic clock input when PLL is not used.
Complementary Clock Input. Used in conjunction with CLK2.
Clock Input. Drives distribution section of the chip.
Complementary Clock Input. Used in conjunction with CLK1.
Multipurpose Input. May be programmed as a reset (RESETB), sync (SYNCB), or power-down (PDB) pin.
This pin is internally pulled down by a 30 kΩ resistor. If this pin is left NC, the part is in reset by default.
To avoid this, connect this pin to V
Output Used to Monitor PLL Status and Sync Status.
Serial Data Clock.
Serial Data I/O.
Serial Data Output.
Serial Port Chip Select.
Ground.
Complementary LVPECL Output.
LVPECL Output.
Complementary LVPECL Output.
LVPECL Output.
Complementary LVDS/Inverted CMOS Output. OUT4 includes a delay block.
LVDS/CMOS Output. OUT4 includes a delay block.
Complementary LVDS/Inverted CMOS Output.
LVDS/CMOS Output.
Complementary LVPECL Output.
LVPECL Output.
Current Set Resistor to Ground. Nominal value = 4.12 kΩ.
Charge Pump Current Set Resistor to Ground. Nominal value = 5.1 kΩ.
Rev. A | Page 20 of 60
S
with a 1 kΩ resistor.