AD9511BCPZ Analog Devices Inc, AD9511BCPZ Datasheet - Page 55

• Manufacturer Part Number: AD9511BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9511BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9511/PCB - BOARD EVAL CLOCK DISTR 48LFCSPAD9511-VCO/PCB - BOARD EVAL CLOCK DISTR 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

APPLICATIONS
USING THE AD9511 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed analog-to-digital converter (ADC) is extremely
sensitive to the quality of the sampling clock provided by the
user. An ADC can be thought of as a sampling mixer; any noise,
distortion, or timing jitter on the clock is combined with the
desired signal at the A/D output. Clock integrity requirements
scale with the analog input frequency and resolution, with
higher analog input frequency applications at ≥14-bit resolution
being the most stringent. The theoretical SNR of an ADC is
limited by the ADC resolution and the jitter on the sampling
clock. Considering an ideal ADC of infinite resolution where
the step size and quantization error can be ignored, the available
SNR can be expressed approximately by
where f is the highest analog frequency being digitized, and t
the rms jitter on the sampling clock. Figure 53 shows the
required sampling clock jitter as a function of the analog
frequency and effective number of bits (ENOB).
See Application Notes AN-756 and AN-501 on the ADI website
at www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection, which can
provide superior clock performance in a noisy environment.)
The AD9511 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. The input
requirements of the ADC (differential or single-ended, logic
120
100
80
60
40
20
SNR
1
FULL-SCALE SINE WAVE ANALOG INPUT FREQUENCY (MHz)
=
Figure 53. ENOB and SNR vs. Analog Input Frequency
20
t j = 0.1ps
×
log
3
⎡
⎢
⎢
⎣
2π
1
t j = 50fs
ft
j
t j = 1ns
⎤
⎥
⎥
⎦
t j = 10ps
t j = 100ps
t j = 1ps
10
SNR = 20log
30
10
2πft j
1
100
18
16
14
12
10
8
6
4
Rev. A | Page 55 of 60
j
is
level, termination) should be considered when selecting the best
clocking/converter solution.
CMOS CLOCK DISTRIBUTION
The AD9511 provides two clock outputs (OUT3 and OUT4),
which are selectable as either CMOS or LVDS levels. When
selected as CMOS, these outputs provide for driving devices
requiring CMOS level logic at their clock inputs.
Whenever single-ended CMOS clocking is used, some of the
following general guidelines should be followed.
Point-to-point nets should be designed such that a driver has
one receiver only on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver. The
value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS
outputs are limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
3 inches are recommended to preserve signal rise/fall times and
preserve signal integrity.
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9511 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 55. The far-
end termination network should match the PCB trace
impedance and provide the desired switching point. The
reduced signal swing can still meet receiver input requirements
in some applications. This may be useful when driving long
trace lengths on less critical nets.
CMOS
Figure 55. CMOS Output with Far-End Termination
Figure 54. Series Termination of CMOS Output
OUT3, OUT4
SELECTED AS CMOS
10Ω
CMOS
10Ω
50Ω
MICROSTRIP
1.0 INCH
60.4Ω
V
PULLUP
50pF
GND
= 3.3V
100Ω
100Ω
AD9511
3pF