AD9511BCPZ Analog Devices Inc, AD9511BCPZ Datasheet - Page 52

• Manufacturer Part Number: AD9511BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9511BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9511/PCB - BOARD EVAL CLOCK DISTR 48LFCSPAD9511-VCO/PCB - BOARD EVAL CLOCK DISTR 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9511
Reg.
Addr.
(Hex)
4A
(4C)
(4E)
(50)
(52)
4A
(4C)
(4E)
(50)
(52)
4B
(4D)
(4F)
(51)
(53)
4B
(4D)
(4F)
(51)
(53)
4B
(4D)
(4F)
(51)
(53)
4B
(4D)
(4F)
(51)
(53)
4B
(4D)
(4F)
(51)
(53)
54 (55)
(56) (57)
58
58
Bit(s) Name
<3:0> Divider High
<7:4> Divider Low
<3:0> Phase Offset
<4>
<5>
<6>
<7>
<7:0>
<0>
<1>
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
Start
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
Force
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
Nosync
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
Bypass Divider
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
SYNC Detect
Enable
SYNC Select
Description
Number of Clock Cycles Divider Output Stays High.
Number of Clock Cycles Divider Output Stays Low.
Phase Offset (Default = 0000b).
Selects Start High or Start Low.
(Default = 0b).
Forces Individual Outputs to the State Specified in Start (Above).
This Function Requires That Nosync (Below) Also Be Set (Default = 0b).
Ignore Chip-Level Sync Signal (Default = 0b).
Bypass and Power-Down Divider Logic; Route Clock Directly to Output (Default = 0b).
Not Used.
1 = Enable SYNC Detect (Default = 0b).
1 = Raise Flag if Slow Clocks Are Out-of-Sync by 0.5 to 1 High Speed Clock Cycles.
0 (Default) = Raise Flag if Slow Clocks Are Out-of-Sync by 1 to 1.5 High Speed Clock Cycles.
Rev. A | Page 52 of 60