IDT5V49EE702NDGI8 IDT, Integrated Device Technology Inc, IDT5V49EE702NDGI8 Datasheet - Page 22

• Manufacturer Part Number: IDT5V49EE702NDGI8
• Description: IC PLL CLK GEN 200MHZ 28VQFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generator, Multiplexerr

Specifications of IDT5V49EE702NDGI8

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: HCSL, LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:7
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: IDT5V49EE702DLGI8; IDT5V49EE702DLGI8

1.Practical lower frequency is determined by loop filter settings.
2.A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3.Jitter measured with clock outputs of 27 MHz, 48 MHz, 24.576 MHz, 74.25 MHz and 25 MHz.
4.Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.
5.Actual PLL lock time depends on the loop configuration.
Spread Spectrum Generation Specifications
1.Practical lower frequency is determined by loop filter settings.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Symbol
Symbol
f
IDT5V49EE702
EEPROM PROGRAMMABLE CLOCK GENERATOR
SPREAD
f
t10
f
MOD
t9
IN
t7
t8
4
1
5
Clock Jitter
Output Skew
Lock Time
Lock Time
Input Frequency Input Frequency Limit
Mod Frequency
Spread Value
Parameter
Parameter
Modulation Frequency
Amount of Spread Value (programmable) - Down Spread
Amount of Spread Value (programmable) - Center Spread
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVTTL outputs
Peak-to-peak period jitter, all 4 PLLs on,
LVTTL outputs
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVPECL, LVDS
or HCSL outputs
Peak-to-peak period jitter, all 4 PLLs on,
LVPECL, LVDS or HCSL outputs
Skew between output to output on the same
bank
PLL lock time from power-up
PLL lock time from shutdown mode
Description
Test Conditions
3
22
Min.
Min
1
Programmable
Programmable
IDT5V49EE702
CLOCK SYNTHESIZER
Typ.
200
120
Typ
80
60
10
33
Max
Max.
400
100
270
160
80
75
20
2
REV F 022310
%f
Unit
MHz
kHz
Units
OUT
ms
ms
ps
ps
ps
ps
ps