IDT5V49EE702NDGI8 IDT, Integrated Device Technology Inc, IDT5V49EE702NDGI8 Datasheet - Page 25

• Manufacturer Part Number: IDT5V49EE702NDGI8
• Description: IC PLL CLK GEN 200MHZ 28VQFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generator, Multiplexerr

Specifications of IDT5V49EE702NDGI8

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: HCSL, LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:7
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: IDT5V49EE702DLGI8; IDT5V49EE702DLGI8

Programming Registers Table
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Addr
0x0C
0x0D
0x1C
0x1D
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
IDT5V49EE702
EEPROM PROGRAMMABLE CLOCK GENERATOR
Register
Default
Value
Hex
00
00
02
02
0F
04
00
00
00
00
10
10
10
10
10
10
00
00
00
00
00
00
01
01
01
01
01
01
00
00
00
00
00
00
10
10
10
10
10
10
CZ0_CFG4
CZ0_CFG5
CZ0_CFG0
CZ0_CFG1
CZ0_CFG2
CZ0_CFG3
CZ1_CFG4
CZ1_CFG5
CZ1_CFG0
CZ1_CFG1
CZ1_CFG2
CZ1_CFG3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SP
SH
7
Reserved
Reserved
OE6
6
A0[3:0]_CFG0
A0[3:0]_CFG1
A0[3:0]_CFG2
A0[3:0]_CFG3
A0[3:0]_CFG4
A0[3:0]_CFG5
IP0[2:0]_CFG4
IP0[2:0]_CFG5
IP0[2:0]_CFG0
IP0[2:0]_CFG1
IP0[2:0]_CFG2
IP0[2:0]_CFG3
IP1[2:0]_CFG4
IP1[2:0]_CFG5
IP1[2:0]_CFG0
IP1[2:0]_CFG1
IP1[2:0]_CFG2
IP1[2:0]_CFG3
Reserved
Reserved
OE5
5
XTCLKSEL
Reserved
OE4
4
N0[7:0]_CFG4
N0[7:0]_CFG5
N0[7:0]_CFG0
N0[7:0]_CFG1
N0[7:0]_CFG2
N0[7:0]_CFG3
Reserved
Reserved
Reserved
Bit #
D0[6:0]_CFG0
D0[6:0]_CFG1
D0[6:0]_CFG2
D0[6:0]_CFG3
D0[6:0]_CFG4
D0[6:0]_CFG5
OS*[6:0]
OE3
25
3
XTAL[4:0]
OE2
2
RZ0[3:0]_CFG4
RZ0[3:0]_CFG5
RZ0[3:0]_CFG0
RZ0[3:0]_CFG1
RZ0[3:0]_CFG2
RZ0[3:0]_CFG3
N0[11:8]_CFG0
N0[11:8]_CFG1
N0[11:8]_CFG2
N0[11:8]_CFG3
N0[11:8]_CFG4
N0[11:8]_CFG5
RZ1[3:0]_CFG4
RZ1[3:0]_CFG5
RZ1[3:0]_CFG0
RZ1[3:0]_CFG1
RZ1[3:0]_CFG2
RZ1[3:0]_CFG3
PLLS*[3:0]
Reserved
SEL[2:0]
OE1
1
HW/SW
OE0
0
IDT5V49EE702
CLOCK SYNTHESIZER
Hardware/Software Mode control
HW/SW - 0=HW, 1=SW
SEL[2:0] - selects configuration in
SW mode
OEx=Output Power Suspend
function for OUTx (‘1’=OUTx will
be suspended on SD/OE pin.
Disable mode is defined by
OEMx bits), ‘0’=outputs enabled
and no association with OE pin
(default).
OS*[6:0] - output suspend, active
low. Overwrites OE setting.
PLLS*[3:0] - PLL Suspend, active
low
SH - shutdown/OE configuration
XTCLKSEL - crystal/clock select.
0=Crytal, 1=ICLK
XTAL[4:0] - crystal cap
PLL0 loop parameter
PLL0 input divider and input sel
D0[6:0] - 127 step Ref Div
D0 = 0 means power down.
N - Feedback Divider
2 - 4095 (values of “0” and “1” are
not allowed) Total feedback with
A, using provided calculation
PLL1 Loop Parameter
Description
REV F 022310