ICS1523M IDT, Integrated Device Technology Inc, ICS1523M Datasheet - Page 13

• Manufacturer Part Number: ICS1523M
• Description: IC VIDEO CLK SYNTHESIZER 24-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizer (IF), Fanout Distribution, Frequency Generatorr

Specifications of ICS1523M

• Pll: Yes
• Input: Clock
• Output: LVPECL, SSTL-3
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/Yes
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 1523M

MDS ICS1523 ZC
11.2 Programming Flow for Modifying PLL and DPA Settings
Integrated Device Technology, Inc.
Decrement Charge
Pump Current
FUNC = regenerated HSYNC, PLL lock status to LOCK (STATUS) pin
Reg0x1:2~0
(Coast disabled, Positive edge of HSYNC, Internal Feedback,
Internal Feedback Divider (0x3 & 0x2) = HTOTAL - 8
DPA Resolution 0x5 = (Value From Note 8 Table)
Required Output Frequency * VCOD < 500 MHz)
VCO Divider 0x1:5~4 = (Maximum value where
Typical Charge Pump Current 0x1:2~0= 011b
No
Program Feedback Divider Reg0x2, Reg0x3
Program Input Control Register Reg0x0
Program Loop Control Register Reg0x1
Select OSC divider value (if needed)
Program Output Control Reg0x6
Program Internal Filter Reg0x4
Select Desired Input Reg0x7:7
Select Internal Filter 0x4:7 = 1
Program OSC Divider Reg0x7
Enable the desired outputs
Determine Horizontal Total
DPA Offset, 0x4:5~0 = 0
Program DPA Reg0x5
PLL LOCKED?
Typically = 41h
Full S/W Reset
Reg0xA = 5Ah
Correct Phase
Relationship?

LOCK Pin or
Read 0x12:1
13
HTOTAL
Tech Support: www.idt.com/go/clockhelp
BEGIN
END
Yes
Yes
Video Clock Synthesizer with I
No
Increment DPA
Reg0x4
Offset
2
C Programmable Delay
Revision 020811
ICS1523