ICS1523M IDT, Integrated Device Technology Inc, ICS1523M Datasheet - Page 6

• Manufacturer Part Number: ICS1523M
• Description: IC VIDEO CLK SYNTHESIZER 24-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizer (IF), Fanout Distribution, Frequency Generatorr

Specifications of ICS1523M

• Pll: Yes
• Input: Clock
• Output: LVPECL, SSTL-3
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/Yes
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 1523M

MDS ICS1523 ZC
Section 4 Register Set Summary
Note 1: Double-buffered register. Working registers are loaded during software PLL reset. See 0x8.
Note 2: Double-buffered register. Working registers are loaded during software DPA reset. See 0x8.
Notes 3~8: See
Index
Reg.
0x0
0x1
0x2
0x3
0x4
0x5
FdBk Div 0
FdBk Div 1
DPA Offset
Control
Control
Control
Name
Input
Loop
DPA
Section 5, “Register Set Details”
Access
Integrated Device Technology, Inc.
R / W
R / W
R / W
R / W
R / W
R / W
DPA_Res0-1
DPA_OS0-5
Metal_Rev
Bit Name
Reserved
VCOD0-1
Reserved
Reserved
Reserved
Func_Sel
FBD8-11
Fbk_Sel
Ref_Pol
Fbk_Pol
CP_Pol
FBD0-7
EnPLS
ICP0-2
Fil_Sel
EnRef
CPen
Bit #
0-2
4-5
6-7
0-7
0-3
4-7
0-5
0-1
2-7
0
1
2
3
4
5
6
7
3
6
7
Reset
Value
FF
0
1
0
F
0
0
1
0
0
0
0
0
0
0
0
0
0
0
3

6
Tech Support: www.idt.com/go/clockhelp
Charge Pump Enable
0=External Enable via COAST Pin, 1=Always Enabled
COAST Pin Charge Pump Enable Polarity
0=Active High, 1=Active Low
External Reference Polarity
0=Positive Edge, 1=Negative Edge
External Feedback Polarity
0=Positive Edge, 1=Negative Edge
External Feedback Select
0=Internal Feedback, 1=External
FUNC Pin Output Select (DPA delayed)
0=Recovered HSYNC, 1=Input HSYNC
Enable PLL Lock/Ref Status Output
0=Disable 1=Enable
1=Enable Ref to Lock/Ref Output
ICP (Charge Pump Current)
Bit 2,1,0=(000 =1 uA, 001 = 2 uA, 010 = 4 uA, 011 = 8 uA,
100 = 16 uA, 101 = 32 uA, 110 = 64 uA, 111 = 128 uA
Reserved
VCO Divider Bit 5,4 =(00 = ÷2, 01=÷4, 10=÷8, 11=÷16)
Reserved
Feedback Divider LSBs (Bit 7, 6, 5, 4, 3, 2, 1, 0)
Actual # of clocks = Programmed value + 8
Feedback Divider MSBs (Bit 11, 10, 9, 8)
Reserved
Dynamic Phase Aligner Offset
Bit 5, 4, 3, 2, 1, 0 = (MUST be < total # of DPA elements)
Reserved
Loop Filter Select (0=External, 1=Internal)
DPA Resolution, Total # of delay elements
Bit 1, 0 = (00 = 16, 01 = 32, 10 = Reserved, 11 = 64)
Metal Mask Revision Number
Video Clock Synthesizer with I
Description
2
C Programmable Delay
Revision 020811
ICS1523
Note
1, 6
1, 7
2, 8
3
3
4
4
1
1
8
6