ICS1523M IDT, Integrated Device Technology Inc, ICS1523M Datasheet - Page 14

• Manufacturer Part Number: ICS1523M
• Description: IC VIDEO CLK SYNTHESIZER 24-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizer (IF), Fanout Distribution, Frequency Generatorr

Specifications of ICS1523M

• Pll: Yes
• Input: Clock
• Output: LVPECL, SSTL-3
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/Yes
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 1523M

MDS ICS1523 ZC
Section 12 Timing Diagrams
Using the DPA above 160 MHz is not recommended. Set DPA_OS = 0 for speeds in excess of 160 MHz to bypass
the DPA. The DPA Resolution Select register (0x5:0~1) is double-buffered. Working registers are loaded only after
a DPA Software reset (0x8=xA)
HSYNC
DPA Offset when
DPA_OS [5-0] = 0
DPA Offset when
DPA_OS [5-0] = 1
DPA Offset when
DPA_OS [5-0] = 2
DPA Offset when
DPA_OS [5-0] = Max
Figure 12-1 DPA Operation
Table 12-1 DPA Offset Ranges
.
.
.
Register 5
1~0
Integrated Device Technology, Inc.
00
01
11
DPA Offset = CLK Period * (# of DPA Elements Selected [0x4:4~0]
Total # of DPA
Elements
(# of DPA Elements Available)[0x5:1-0]
Fixed delay − See
1 unit of DPA delay
16
32
64
2 units of DPA delay
Maximum units of DPA delay
One full speed clock period

14
Selected #
Figure 12-2
Maximum
Tech Support: www.idt.com/go/clockhelp
Elements
Video Clock Synthesizer with I
0x4:5-0
of DPA
0F
1F
3F
and
Figure 12-3
DPA Clock Range in MHz
Min
48
24
12
1 unit of DPA delay
2
C Programmable Delay
Max
160
80
40
Revision 020811
ICS1523