PEF80902HV1.1XT Infineon Technologies, PEF80902HV1.1XT Datasheet - Page 17

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PEF80902HV1.1XT

Manufacturer Part Number
PEF80902HV1.1XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF80902HV1.1XT

Lead Free Status / Rohs Status
Compliant
Table 2
Pin
44
41
3
4
34
12
27
35
10,11,
16,17,
26,38
PU: Internal pull-up resistor (typ. 100µA)
I: Input
O: Output (Push-Pull)
OD: Output (Open Drain)
1.6.1
LED Pins ACT, LP2I
A LED can be connected to pin ACT to display four different states (off, slow flashing,
fast flashing, on). It displays the activation status of the U- and S-transceiver according
to
Data Sheet
Table
3.
Specific Pins and Test Modes
Pin Definitions and Functions (cont’d)
Symbol
AOUT
BOUT
AIN
BIN
VDDDET
ACT
TP1
TP2
Type
O
O
I
I
I
O
I
I
Function
Differential U-interface Output
Differential U-interface Output
Differential U-interface Input
Differential U-interface Input
VDD Detection:
This pin selects if the V
(’0’) and reset pulses are generated on pin
RSTO or whether it is deactivated (’1’) and an
external reset has to be applied on pin RST.
Activation LED.
Indicates the activation status of U- and S-
transceiver. Can directly drive a LED (4mA).
Test Pin 1.
Used for factory device test.
Tie to ’V
Test Pin 2.
Used for factory device test.
Tie to ’V
Tie to ‘1‘
9
SS
SS
DD
detection is active
PEF 80902
2001-11-12
Overview

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