LU82551ER 860613 Intel, LU82551ER 860613 Datasheet - Page 24

• Manufacturer Part Number: LU82551ER 860613
• Manufacturer: Intel

Specifications of LU82551ER 860613

• Lead Free Status / Rohs Status: Supplier Unconfirmed

82551ER — Networking Silicon
5.2
5.2.1
5.2.1.1
16
Table 10. Initialization Effects
PCI Interface
Bus Operations
After configuration, the 82551ER is ready for its normal operation. As a Fast Ethernet Controller,
the role of the 82551ER is to access transmitted data or deposit received data. In both cases the
82551ER, as a bus master device, will initiate memory cycles by way of the PCI bus.
To perform these actions, the 82551ER is controlled and examined by the CPU through its control
and status structures and registers. Some of these structures reside in the 82551ER and some reside
in system memory. For access to the 82551ER’s Control/Status Registers (CSR), the 82551ER acts
as a slave device. The 82551ER serves as a slave also while the CPU accesses its 128 KB Flash
buffer or its EEPROM.
Section 5.2.1.1
82551ER operation as a bus master (initiator) in
Bus Slave Operation
The 82551ER serves as a target device in the following cases:
The CSR and the 1 MB Flash buffer are considered by the 82551ER as totally separated memory
spaces. The 82551ER provides separate Base Address Registers (BARs) in the configuration space
to distinguish between them. The size of the CSR memory space is 4 KB in the memory space and
64 bytes in the I/O space. The 82551ER treats accesses to these memory spaces differently.
Power
management
event reset
Statistic
counters reset
Sampling of
configuration
input pins
•
•
•
•
•
•
CPU accesses to the 82551ER System Control Block (SCB) Control/Status Registers (CSR)
CPU accesses to the EEPROM through its CSR
CPU accesses to the 82551ER PORT address through the CSR
CPU accesses to the MDI control register in the CSR
CPU accesses to the Flash control register in the CSR
CPU accesses to the 128 KB Flash
describes the 82551ER slave operation. It is followed by a description of the
Internal
POR
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ALTRST#
?
?
?
Clear only
auxiliary
present
power
RST#
if no
?
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Section
ISOLATE#
Clear only
auxiliary
present
power
if no
--
5.2.1.2.
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Transition
D3 to D0
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--
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Software
Reset
--
--
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Datasheet
Selective
Reset
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