LU82551ER 860613 Intel, LU82551ER 860613 Datasheet - Page 6

• Manufacturer Part Number: LU82551ER 860613
• Manufacturer: Intel

Specifications of LU82551ER 860613

• Lead Free Status / Rohs Status: Supplier Unconfirmed

82551ER — Networking Silicon
13.0
Figures
Tables
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Reference Schematics ..................................................................................................... 94
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82551ER Component Markings ............................................................................ 2
CSR I/O Read Cycle ........................................................................................... 17
CSR I/O Write Cycle ........................................................................................... 18
Flash Buffer Read Cycle ..................................................................................... 19
Flash Buffer Write Cycle ..................................................................................... 20
PCI Retry Cycle................................................................................................... 21
Memory Read Burst Cycle .................................................................................. 22
Memory Write Burst Cycle .................................................................................. 22
Initialization upon RST# and ISOLATE# ............................................................. 28
64-Word EEPROM Read Instruction Waveform ................................................. 31
Auto-Negotiation and Parallel Detect .................................................................. 38
Two and Three LED Schematic Diagram............................................................ 39
PCI Configuration Registers................................................................................ 41
PCI Command Register ...................................................................................... 42
PCI Status Register............................................................................................. 43
Cache Line Size Register.................................................................................... 45
Base Address Register for Memory Mapping ..................................................... 46
Base Address Register for I/O Mapping.............................................................. 46
Control/Status Register ....................................................................................... 53
PCI Clock Waveform ........................................................................................... 81
Output Timing Measurement Conditions............................................................. 82
Input Timing Measurement Conditions ............................................................... 82
Flash Timings for a Read Cycle .......................................................................... 85
Flash Timings for a Write Cycle .......................................................................... 85
EEPROM Timings ............................................................................................... 86
10BASE-T Normal Link Pulse (NLP) Timings ..................................................... 87
Auto-Negotiation Fast Link Pulse (FLP) Timings ................................................ 87
Dimension Diagram for the 196-pin BGA ............................................................ 89
196 PBGA Package Pad Detail........................................................................... 90
Ball Grid Array Diagram ...................................................................................... 93
Reference Schematic Layout (Sheet 1 of 2) ....................................................... 95
Reference Schematic Layout (Sheet 2 of 2) ....................................................... 96
RJ-45 Connections................................................................................................ 6
Signal Type Descriptions ...................................................................................... 7
Address and Data Signals..................................................................................... 8
Interface Control Signals....................................................................................... 8
System and Power Management Signals ............................................................. 9
Local Memory Interface Signals .......................................................................... 10
Test Port Signals ................................................................................................. 11
PHY Signals ........................................................................................................ 12
Power and Ground Signals ................................................................................. 13
Initialization Effects ............................................................................................. 15
Datasheet