LU82551ER 860613 Intel, LU82551ER 860613 Datasheet - Page 30

• Manufacturer Part Number: LU82551ER 860613
• Manufacturer: Intel

Specifications of LU82551ER 860613

• Lead Free Status / Rohs Status: Supplier Unconfirmed

82551ER — Networking Silicon
5.2.1.2
22
Figure 7. Memory Read Burst Cycle
Figure 8. Memory Write Burst Cycle
Note: The 82551ER detects a system error for any parity error during an address phase, whether or not it
is involved in the current transaction.
Bus Master Operation
As a PCI Bus Master, the 82551ER initiates memory cycles to fetch data for transmission or
deposit received data and to access the memory resident control structures. The 82551ER performs
zero wait state burst read and write cycles to the host main memory.
memory read and write burst cycles. For bus master cycles, the 82551ER is the initiator and the
host main memory (or the PCI host bridge, depending on the configuration of the system) is the
target.
The CPU provides the 82551ER with action commands and pointers to the data buffers that reside
in host main memory. The 82551ER independently manages these structures and initiates burst
memory cycles to transfer data to and from them. The 82551ER uses the Memory Read Multiple
(MR Multiple) command for burst accesses to data buffers and the Memory Read Line (MR Line)
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
1
1
MW
MR
ADDR
ADDR
2
2
3
3
DATA
DATA
BE#
BE#
4
4
DATA
DATA
5
5
DATA
DATA
6
6
DATA
DATA
BE#
BE#
7
7
Figure 7
DATA
DATA
8
8
and
9
9
Figure 8
10
10
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