LU82551ER 860613 Intel, LU82551ER 860613 Datasheet - Page 35

• Manufacturer Part Number: LU82551ER 860613
• Manufacturer: Intel

Specifications of LU82551ER 860613

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Datasheet
Note: A separate internal power-on reset signal is generated when power is applied to the device. This
5.3.1.4.1 Auxiliary Power Signal
The 82551ER senses whether it is connected to the PCI power supply or to an auxiliary power
supply (V
with FLA1) is sampled when the 82551ER power-on reset is active. An external pull-up resistor
should be connected to the 82551ER if it is fed by V
should be left floating. The presence of AUXPWR affects the value reported in the Power
Management Capability Register (PCI Configuration Space, offset DEh). The Power Management
Capability Register is described in more detail in
Register”.
5.3.1.4.2 Alternate Reset Signal
The 82551ER’s ALTRST# input pin functions as a power-on reset input. Following ALTRST#
being driven low, the 82551ER is initialized to a known state. While this function is required, this
pin is not needed for it. Since this functionality is provided by the 82551ER’s internal power-on
reset signal, this pin should be pulled high to the main digital power supply.
signal is active while it provides the 82551ER power-on reset function and is also used for
sampling configuration inputs.
5.3.1.4.3 Isolate Signal
When the 82551ER is connected to V
In this case, the 82551ER isolates itself from the PCI bus. The 82551ER has a dedicated
ISOLATE# pin that must be connected to the PCI Reset signal. Whenever the PCI Bus is in the B3
state, the PCI Reset signal becomes active and the 82551ER isolates itself from the PCI bus.
During this state, the 82551ER ignores all PCI signals including the RST# and CLK input signals.
It also tristates all PCI outputs, except the PME# signal. In the transition to an active PCI power
state (in other words, from B3 bus power state to B0 bus power state), the PCI Reset signal shifts
high. This generates an internal hardware reset, which initializes the device (described in
5.1.1, “Initialization
Some designs in existence may implement the previous recommendations for the RST#,
ISOLATE# and ALTRST# input pins. In these cases, the PCI Reset signal is connected to the RST#
pin, the PCI power source’s stable power (power good) to the ISOLATE# pin, and the auxiliary
power source’s stable power (auxiliary power good) to the ALTRST# pin. It is not necessary for
existing working designs to make changes for these signals; however, it is recommended that the
changes contained in this document should be included when possible. New designs should
implement the recommendations contained in this document.
5.3.1.4.4 PCI Reset Signal
The PCI RST# signal can be activated in one of the following cases:
•
•
•
•
Power-up
Warm boot
Wake-up (B3 to B0 transition)
Set to power-down (B0 to B3 transition)
AUX
) through the FLA1/AUXPWR pin. The auxiliary power detection pin (multiplexed
Effects”).
AUX
, it can be powered on while the PCI bus is powered off.
Section 7.1.19, “Power Management Capabilities
AUX
; otherwise, the FLA1/AUXPWR pin
Networking Silicon — 82551ER
Section
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