LU82551ER 860613 Intel, LU82551ER 860613 Datasheet - Page 36

• Manufacturer Part Number: LU82551ER 860613
• Manufacturer: Intel

Specifications of LU82551ER 860613

• Lead Free Status / Rohs Status: Supplier Unconfirmed

82551ER — Networking Silicon
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Figure 9. Initialization upon RST# and ISOLATE#
Note: The PCI Specification, Revision 2.2, states that the PCI RST# signal should be active low in the B3
If PME# is enabled (in the PCI power management registers), the RST# signal does not affect any
PME# related circuits (in other words, the PCI power management registers, and the wake-up
packet would not be affected).
state. (In PCI Specification, Revision 2.1, the PCI RST# signal is undefined during the B3 state.)
The transition from the B3 bus power state to the B0 bus power state occurs on the trailing edge of
the PCI RST# signal.
The initialization signal is generated internally in the following cases:
The internal initialization signal resets the PCI Configuration Space, MAC configuration, and
memory structure.
The behavior of the RST# and ISOLATE# pins and the internal 82551ER initialization signal are
shown in the following figure.
•
•
•
Active RST# signal while the 82551ER is the D0, D1, or D2 power state
RST# trailing edge while the 82551ER is in the D3 power state
ISOLATE# trailing edge
RST#
Internal hardware
reset
RST#
Internal hardware
reset
ISOLATE#
Internal hardware
reset
D0 - D2 power state
Internal reset
due to ISOLATE#
D3 power state
640 ns
640 ns
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