S2064A Applied Micro Circuits Corporation, S2064A Datasheet

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S2064A

Manufacturer Part Number
S2064A
Description
Manufacturer
Applied Micro Circuits Corporation
Datasheet

Specifications of S2064A

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.13V
Operating Supply Voltage (max)
3.47V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Lead Free Status / Rohs Status
Not Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
S2064A
Manufacturer:
AMCC
Quantity:
1 238
FEATURES
APPLICATIONS
Figure 1. Typical Quad Gigabit Ethernet Application
October 13, 2000 / Revision G
DEVICE
SPECIFICATION
S2064 QUAD SERIAL BACKPLANE DEVICE
QUAD SERIAL BACKPLANE DEVICE
INTERFACE
• Broad operating rate range (0.7 - 1.3 GHz)
• Quad Transmitter with phase-locked loop (PLL)
• Quad Receiver PLL provides clock and data
• Internally series terminated TTL outputs
• On-chip 8B/10B line encoding and decoding for
• 32-bit parallel TTL interface
• Low-jitter serial PECL interface
• Local Loopback
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 2.3 W power dissipation
• Compact 23mm x 23mm 208 TBGA package
• Ethernet Backbones
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
ETHERNET
– 1062 MHz (Fibre Channel)
– 1250 MHz (Gigabit Ethernet) line rates
– 1/2 Rate Operation
clock synthesis from low speed reference
recovery
four separate parallel 8-bit channels
GIGABIT
QUAD
GE INTERFACE
S2066
GENERAL DESCRIPTION
The S2064 facilitates high-speed serial transmission
of data in a variety of applications including Gigabit
Ethernet, Fibre Channel, serial backplanes, and pro-
prietary point to point links. The chip provides four
separate transceivers which can be operated indi-
vidually or locked together for an aggregate data
capacity of >4 Gbps.
Each bi-directional channel provides 8B/10B coding/
decoding, parallel to serial and serial to parallel con-
version, clock generation/recovery, and framing. The
on-chip transmit PLL synthesizes the high-speed
clock from a low-speed reference. The on-chip quad
receive PLL is used for clock recovery and data re-
timing on the four independent data inputs. The
transmitter and receiver each support differential
PECL-compatible I/O for copper or fiber optic com-
ponent interfaces with excellent signal integrity. Lo-
cal loopback mode allows for system diagnostics.
The chip requires a 3.3V power supply and dissi-
pates approximately 2.3 watts.
Figure 1 shows the S2064 and S2066 in a Gigabit
Ethernet application. Figure 2 combines the
S2064 with a crosspoint switch to demonstrate a
serial backplane application. Figure 3 is the input/
output diagram. Figures 4 and 5 show the transmit
and receive block diagrams, respectively.
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
SERIAL BP DRIVER
S2064
TO SERIAL BACKPLANE
S2064
S2064
®
1

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S2064A Summary of contents

Page 1

DEVICE SPECIFICATION S2064 QUAD SERIAL BACKPLANE DEVICE QUAD SERIAL BACKPLANE DEVICE FEATURES • Broad operating rate range (0.7 - 1.3 GHz) – 1062 MHz (Fibre Channel) – 1250 MHz (Gigabit Ethernet) line rates – 1/2 Rate Operation • Quad Transmitter ...

Page 2

S2064 Figure 2. Typical Backplane Application MAC (ASIC) MAC ATM (ASIC) Fibre S2064 Channel Ethernet MAC Etc. (ASIC) MAC (ASIC) MAC (ASIC) ATM MAC Fibre (ASIC) Channel S2064 Ethernet MAC Etc. (ASIC) MAC (ASIC) 2 QUAD SERIAL BACKPLANE DEVICE Crosspoint ...

Page 3

S2064 QUAD SERIAL BACKPLANE DEVICE Figure 3. S2064 Input/Output Diagram RESET RATE REFCLK CLKSEL TMODE TCLKO DINA[0:7] 10 SOFA, KGENA TCLKA DINB[0:7] 10 SOFB, KGENB TCLKB DINC[0:7] 10 SOFC, KGENC TCLKC DIND[0:7] 10 SOFD, KGEND TCLKD EOFA DOUTA[0:7] 10 ERRA, ...

Page 4

S2064 Figure 4. Transmitter Block Diagram RATE REFCLK CLKSEL CH_LOCK TMODE 8 DINA[ 0:7 ] FIFO SOFA (input) KGENA TCLKA 8 DINB[ 0:7 ] FIFO (input) SOFB KGENB TCLKB 8 DINC[ 0:7 ...

Page 5

S2064 QUAD SERIAL BACKPLANE DEVICE Figure 5. Receiver Block Diagram RATE CMODE REFCLK EOFA KFLAGA FIFO (output) ERRA 8 Q DOUTA[0:7] 2 RCAP/N EOFB KFLAGB FIFO (output) ERRB 8 DOUTB[0:7] 2 RCBP/N EOFC KFLAGC FIFO (output) ERRC 8 DOUTC[0:7] 2 ...

Page 6

S2064 TRANSMITTER DESCRIPTION The transmitter section of the S2064 contains a single PLL which is used to generate the serial rate transmit clock for all transmitters. Four channels are provided with a variety of options regarding input clocking and loopback. ...

Page 7

S2064 QUAD SERIAL BACKPLANE DEVICE Figure 6. DIN Data Clocking with TCLK TCLKO DINx[0:7] TCLKx MAC ASIC The S2064 also supports the traditional REFCLK (TBC) clocking found in Fibre Channel and Gigabit Ethernet application and is illustrated in Figure 7. ...

Page 8

S2064 In addition to data and K characters, the S2064 can also generate a unique sync sequence consisting of 16 consecutive K28.5 characters. This event is initi- ated by the simultaneous assertion of KGENx and SOFx for one clock period. ...

Page 9

S2064 QUAD SERIAL BACKPLANE DEVICE Table 2. K Character Generation (SOFx = ...

Page 10

S2064 RECEIVER DESCRIPTION Each receiver channel is designed to implement a Serial Backplane receiver function through the physi- cal layer. A block diagram showing the basic func- tion is provided in Figure 5. Whenever a signal is present, the receiver ...

Page 11

S2064 QUAD SERIAL BACKPLANE DEVICE Serial to Parallel Conversion Once bit synchronization has been attained by the S2064 CRU, the S2064 must synchronize to the 10 bit word boundary. Word synchronization in the S2064 is accomplished by detecting and aligning ...

Page 12

S2064 Figure 8. Channel Lock State Machine All four channels in Re-Sync with valid data within deskew window RE-SYNC Figure 9. Channel Lock Synchronization Timing (Internal) RESYNC A (Internal) RESYNC B (Internal) RESYNC C (Internal) RESYNC D (internal) deskewed RESYNC ...

Page 13

S2064 QUAD SERIAL BACKPLANE DEVICE Table 6. Error and Status Reporting ...

Page 14

S2064 CHANNEL LOCKING/RE-LOCKING PROCEDURE The Channel locking/relocking procedures are sum- marized below. Following these procedures will in- sure proper CHANNEL LOCK operation of the device. When powered up, the S2064 will lock to the received data within approximately 2500 bit ...

Page 15

S2064 QUAD SERIAL BACKPLANE DEVICE OTHER OPERATING MODES Operating Frequency Range The S2064 is designed to operate at serial baud rates of 0.77 GHz to 1.3 GHz (800 Mbps to 1064 Mbps user data rate). The part is specified at ...

Page 16

S2064 Table 8. S2064 Transmitter Input Pin Assignment and Descriptions ...

Page 17

S2064 QUAD SERIAL BACKPLANE DEVICE Table 8. Transmitter Signal Descriptions (Continued ...

Page 18

S2064 Table 10. S2064 Mode Control Signals ...

Page 19

S2064 QUAD SERIAL BACKPLANE DEVICE Table 11. S2064 Receiver Output Pin Assignment and Descriptions ...

Page 20

S2064 Table 11. S2064 Receiver Output Pin Assignment and Descriptions (Continued ...

Page 21

S2064 QUAD SERIAL BACKPLANE DEVICE Table 12. S2064 Receiver Input Pin Assignment and Descriptions ...

Page 22

S2064 Table 14. Power and Ground Signals ...

Page 23

S2064 QUAD SERIAL BACKPLANE DEVICE Figure 11. S2064 Pinout (Bottom View ...

Page 24

S2064 Figure 12. S2064 Pinout (Top View ...

Page 25

S2064 QUAD SERIAL BACKPLANE DEVICE Figure 13. Compact 23mm x 23mm 208 TBGA Package Thermal Management October 13, 2000 / Revision ...

Page 26

S2064 Figure 14. Transmitter Timing (Normal or Channel Lock Mode, TMODE = 0) REFCLK DINx[0:7], SOFx, KGENx SERIAL DATA OUT Table 15. S2064 Transmitter Timing (Normal or Channel Lock Mode, TMODE = ...

Page 27

S2064 QUAD SERIAL BACKPLANE DEVICE Figure 16. Receiver Timing (Full Clock Mode, CMODE = 1) SERIAL DATA IN RCxN RCxP DOUTx[0:7], EOFx, KFLAGx, ERRx Figure 17. Receiver Timing (Half Clock Mode, CMODE = 0) SERIAL DATA IN RCxN RCxP DOUTx[0:7], ...

Page 28

S2064 Figure 18. TCLKO Timing REFCLK TCLKO Table 18. S2064 Transmitter (TCLKO Timing Note: Measurements are made at 1.4V level of ...

Page 29

S2064 QUAD SERIAL BACKPLANE DEVICE Table 19. Absolute Maximum Ratings ...

Page 30

S2064 Table 22. Serial Data Timing, Transmit Outputs ...

Page 31

S2064 QUAD SERIAL BACKPLANE DEVICE OUTPUT LOAD The S2064 serial outputs require a resistive load to set the output current. The recommended resistor value is 4 ground. This value can be varied to adjust drive current, signal voltage ...

Page 32

S2064 Figure 25. Loop Filter Capacitor Connections 32 QUAD SERIAL BACKPLANE DEVICE 270 CAP1 22 nf CAP2 270 S2064 October 13, 2000 / Revision G ...

Page 33

... Ordering Information Grade S – Commercial Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 • (800) 755-2622 • Fax: (858) 450-9885 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current ...

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