S2064A Applied Micro Circuits Corporation, S2064A Datasheet - Page 8

• Manufacturer Part Number: S2064A
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S2064A

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

In addition to data and K characters, the S2064 can
also generate a unique sync sequence consisting of
16 consecutive K28.5 characters. This event is initi-
ated by the simultaneous assertion of KGENx and
SOFx for one clock period. The SOFx and KGENx
inputs should be held low until the sync sequence
has completed. The sync sequence may start with
either a positive or negative parity K28.5. (Depend-
ing on the current running disparity.) The parity of
the second and third K28.5 are inverse with respect
to a valid 8B/10B sequence. Parity of the remaining
K28.5 alternate in accordance with the 8B/10B cod-
8
S2064
Table 1b. Transmitter Control Signals (Channel Lock Mode, CH_LOCK = 1)
S
O
X
0
0
1
1
F
Table 1a. Transmitter Control Signals (Normal Mode, CH_LOCK = 0)
A
S
O
0
0
1
1
F
S
x
O
0
0
0
0
1
F
B
K
G
E
0
1
0
1
K
N
G
x
X
0
1
0
1
E
N
E
K
I D
K
S
+
- -
x
n
2
p
+
C
[ N
c
8
e
+
h
o
5 .
c
- -
: 7
E
K
K
S
S
c
+
d
a
l a i
h
n
2
p
p
e
a r
] 0
C
C
a
+
-
c
8
e
e
d
n
1
t c
h
+
o
h
5 .
c
c
-
6
n
a
d
a
l a i
l a i
P
r e
+
-
e
a r
a r
e
C
r a
w
+
. s l
d
-
1
1
h
a
t c
t c
o
l a
+
-
6
6
S
a
s
P
d r
ing standard. Thus the parity of the K28.5 pattern
consists of + + - - + - + - + - + - + - + - or - - + + - + -
+ - + - + - + - +. Tables 1a and 1b show the transmit-
ter control signals for both Normal and Channel Lock
mode.
Frequency Synthesizer (PLL)
The S2064 synthesizes a serial transmit clock from
the reference signal. Upon startup, the S2064 will
obtain phase and frequency lock within 2500 bit
times after the start of receiving reference clock in-
puts. Reliable locking of the transmit PLL is assured,
but a lock-detect output is NOT provided.
r e
r e
l e l
+
a r
2
r a
-
W
W
d
0
c
f e
+
-
a
t c
l a
o
o
6
D
h
s
+
r e
4
n i
d r
d r
a
-
l e l
a
QUAD SERIAL BACKPLANE DEVICE
d
a r
+
-
a t
e
D
f e
o
S
S
d
+
S
D
c
N I
-
n
y
y
n i
2
e t
t a
b
+
-
n
n
l l a
0
e
y
, r
+
c
c
O
. a
-
6
d
T
4
u
r o
C
C
o f
b
a
p t
h
h
O
y
r u
b
a
a
t u
e l
u
T
a r
a r
c
p t
a
h
2
t c
t c
b
t u
a
e l
r e
r e
a
n
n
n
2
d
o
o
e
n
n
o
. s l
n
October 13, 2000 / Revision G
c
l l a
h
c
a
h
o f
n
a
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n
l e
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. x
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