S2064A Applied Micro Circuits Corporation, S2064A Datasheet - Page 11

• Manufacturer Part Number: S2064A
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S2064A

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

Serial to Parallel Conversion
Once bit synchronization has been attained by the
S2064 CRU, the S2064 must synchronize to the 10
bit word boundary. Word synchronization in the
S2064 is accomplished by detecting and aligning to
the 8B/10B K28.5 codeword. The S2064 will detect
and byte-align to either polarity of the K28.5. Each
channel of the S2064 will detect and align to a K28.5
anywhere in the data stream. Two modes of opera-
tion are supported. For NORMAL mode operation,
the presence of a K28.5 is indicated for each chan-
nel by the assertion of the EOFx signal.
For CHANNEL LOCK operation, the S2064 must
provide an additional level of synchronization to in-
sure that differences in delay encountered by the
four channels do not result in parallel output data
from each channel leading or lagging by one parallel
clock cycle. In CHANNEL LOCK, 10 bit mode, asser-
tion of SOFA results in the K28.5 being transmitted
simultaneously on all four channels. Each receiver
provides a FIFO buffer and adjusts the delay through
this buffer to insure that the first data following the
K28.5 is output simultaneously from the receiver on
the parallel interface. The reception of a K28.5 char-
acter is indicated on the EOFA signal. Table 6 de-
tails the function of the EOF, KFLAG, and ERR pins
in status reporting. For CHANNEL LOCK operation,
a single output clock, RCAP/N, is provided synchro-
nous with the data. The other RCxP/N clocks will be
frequency locked, but will have an arbitrary phase
relationship with the data.
Channel Lock Mode Synchronization
Incidental errors occurring in the received data can
transform a normal data character into a K28.5 char-
acter. To prevent this occurrence from making the
channel locking process unnecessarily vulnerable to
bit errors, the S2064 implements a channel lock
state machine for each channel with linkage between
channels to move to the final de-skewed state.
The Channel Lock state diagram is shown in Figure
8. The S2064 powers up in the “No Sync” state.
When in the “No Sync” state, each channel of the
S2064 is actively searching the received data stream
for the occurrence of a K28.5 and will align its de-
multiplexor to the character when detected, and will
enter the “Acquiring Sync” state. K28.5 will be re-
ported on each channel as 0-1-1 (err-eof-kflag).
October 13, 2000 / Revision G
S2064 QUAD SERIAL BACKPLANE DEVICE
When four or more consecutive K28.5 characters are
received on a given channel, the channel will enter
the “Re-sync” state as shown in Figure 8. “Re-Sync”
state status will not be reported as 1-1-1 until the
first valid data character has been received. If all
four channels are in the “Re-sync” state and each
has received a valid data character within the
deskew time of 5 bytes, then the S2064 will channel
lock by aligning the data output from each channel
such that the first valid data character for each chan-
nel is output simultaneously. The device will move to
the “In Sync” state and indicate channel lock status
by each channel as a 0-1-0. Note that “Re-sync” is
reported independently by each channel regardless
of the state of the other channels. However, “In
Sync” can only be reported when all four channels
are in the “In Sync” state and detect a valid data
character within the deskew window. The “In Sync”
state is reported for each as 0-1-0.
Once the S2064 has entered the “In Sync” state, it will
report status but will not alter the relative skew of the
output FIFOs. The S2064 will exit the “In Sync” state
and move to the “No Sync” state if one of the four
CRUs reports a loss of lock, if the 8B/10B decoder
observes four consecutive decoding errors, or if the
decoder error rate >50% in a block of 16 codewords.
The device can also be put in the “No Sync” state by
setting SOFD=Low, asserting RESET, or by momen-
tarily de-asserting CH_LOCK signal.
SOFD is used to reset the Channel Lock state ma-
chine and provides minimum disruption of the data
path.
When not in Channel Lock Mode, the linkage be-
tween the four state machines is broken and each
channel operates independently.
Loss of Channel Lock will be reported as indicated in
Figure 9 and Table 6 by a 1-0-1 on the ERR, EOF,
and KFLAG signals, respectively. This is during the
“No Sync” state. The status lines will reflect the status
of the individual channels and the device will respond
to appropriate channel locking sequences and
deskew as necessary. Persistence of 1-0-1 status on
any channel is indicative of CRU lock failure, most
likely resulting from loss of receiver input signal. The
device will then respond to the channel locking se-
quence.
When operating in the Channel Lock Mode, the
TCLK[B-D] inputs must be tied low.
S2064
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