EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 19

IC CYCLONE III FPGA 55K 484FBGA

EP3C55F484C8N

Manufacturer Part Number
EP3C55F484C8N
Description
IC CYCLONE III FPGA 55K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C55F484C8N

Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2396160
Number Of I /o
327
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
55856
# I/os (max)
327
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
55856
Ram Bits
2396160
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
3491
Family Type
Cyclone III
No. Of I/o's
327
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2510

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Chapter 1: Cyclone III Device Data Sheet
Electrical Characteristics
© January 2010 Altera Corporation
Example 1–1
from 25°C at 3.0 V to 85°C at 3.15 V:
Example 1–1.
Because ΔR
Because ΔR
Pin Capacitance
Table 1–9
Table 1–9. Cyclone III Devices Pin Capacitance
C
C
C
C
C
C
C
Notes to
(1) When VREF pin is used as regular input or output, a reduced performance of toggle rate and t
(2) C
Symbol
IOTB
IOLR
LV DSLR
V REFLR
V REFTB
C LKTB
C LKLR
MF
MF
MF = 0.963 × 1.157 = 1.114
R
higher pin capacitance.
VREFTB
final
ΔR
ΔR
(1)
(1)
V
T
Table
= 15.72/100 + 1 = 1.157
= 1 / (3.83/100 + 1) = 0.963
= 50 × 1.114 = 55.71 Ω
V
T
= (3.15 – 3) × 1000 × –0.026 = –3.83
= (85 – 25) × 0.262 = 15.72
for EP3C25 is 30 pF.
lists the pin capacitance for Cyclone III devices.
V
T
Input capacitance on top/bottom I/O pins
Input capacitance on left/right I/O pins
Input capacitance on left/right I/O pins with dedicated
LVDS output
Input capacitance on left/right dual-purpose VREF pin
when used as V
Input capacitance on top/bottom dual-purpose VREF pin
when used as V
Input capacitance on top/bottom dedicated clock input
pins
Input capacitance on left/right dedicated clock input pins
is negative,
is positive,
1–9:
shows you the example to calculate the change of 50 Ω I/O impedance
REF
REF
or user I/O pin
or user I/O pin
Parameter
Cyclone III Device Handbook, Volume 2
Typical –
23
QFP
21
7
8
7
7
6
(2)
Typical –
C O
23
FBGA
is expected due to
21
6
5
7
6
5
(2)
Unit
pF
pF
pF
pF
pF
pF
pF
1–9

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